Challenges successfully overcome in scaling MirrorBit technology to the 45-nm node include short-channel effect and program disturb. Junction engineering, bitline trench architecture, and biasing conditions/algorithms were the key areas of optimization.
The effect of cycling and bake on data retention is shown in figure 5. The end-of-life window is sufficient for highly reliable, two-bits-per-cell operation, and MirrorBit products are qualified to meet the requirements of consumer, industrial, as well as automotive applications. Figure 6 shows the ability to cycle a MirrorBit array more than one million times. Overall, MirrorBit has been shown to be an excellent technology for scaling, performance, and reliability.
Figure 5: Effect of cycling plus data-retention bake on MirrorBit showing good end-of-life window.
Figure 6: More than one-million cycles demonstrated on MirrorBit array with erase time maintained within spec.
Heterogeneous charge-trap NAND flash
The demand for increasing density of NAND has been driving rapid technology scaling. However, scaling the conventional FG NAND technology beyond 20nm node poses severe challenges such as gate-coupling degradation and inter-cell interference . In addition, as the space between adjacent bitlines shrinks, it becomes physically impossible to fit the ONO inter-poly dielectric and the control-gate poly between the floating gates (see figure 7).
Figure 7: The inability to place ONO in the shrinking space between floating gates will limit the scaling of FG NAND much beyond 20 nm, even with sloping floating-gate profile.
Planar NAND cells are expected to be more scalable than traditional FG. However, planar cells like TANOS  and hybrid FG  involve complex process modules such as metal gate and high-k dielectric. Spansion’s Heterogeneous Charge Trap (HCT) NAND, on the other hand, is the industry’s first production-worthy and manufacturable planar charge-trap NAND technology.
To improve the Fowler Nordheim tunneling-based program and erase performance, the heterogeneous charge-trap film has been engineered as a multilayered nitride stack with varying silicon contents. HCT film is conductive and therefore isolated for each memory cell. HCT NAND achieves this through a self-aligned isolation technique which adds to the ease of scaling.
TEMs of the 43-nm core cell in both wordline and bitline directions are shown in figure 8. Extending the HCT film beyond the source/drain (SD) edge effectively suppresses the fringing field, thereby preventing SD corner turn-on and STS degradation .
Figure 8. TEMs of HCT NAND core cell in WL and BL directions.
When scaling to smaller dimensions, HCT NAND provides significant advantage over FG NAND in terms of inter-cell interference. The tall storage node of floating gate is a serious problem for capacitive coupling across wordlines. In contrast, HCT has negligible interference from cells along the same wordline (see figure 9). Similarly, the interference along the same bitline is also negligible (see figure 10).
Figure 9: No Program Disturb on inhibited cells in the programmed wordline (with 8x partial-page programming), indicating excellent self-boosting. Very small (about 200 mV) interference is seen when both adjacent bitlines are programmed. To accentuate the interference, the programming bias condition was stronger than in normal operation.
Figure 10: Negligible interference when cells in adjacent word-lines are programmed.
In FG NAND, a program disturb occurs at small dimensions where a high field is induced on the floating gate next to the program wordline . This high field occurs at the corner of the FG, as shown in Figure 11a and causes charge loss from programmed cells. On the other hand, the electric field at the adjacent storage node in HCCT NAND is significantly lower: 7MV/cm compared to 222 MV/cm, at the 16-nm node simulated in figure 11. Thus, HHCT NAND is less prone to program interference.
Figure 11: Simulated comparison at 16-nm node. Program interference field
for FG NAND (a) is three times higher than that of HCT NAND (b) under
the same programming bias condition.