With the rapid growth in automotive electronics, a wide range of semiconductor devices now have to meet very high quality and reliability requirements. These requirements are being driven by new standards, such as ISO 26262 and IEC 61508. To ensure adherence to these strict standards for safety-critical automotive electronics, some key improvements to traditional test methodologies are needed, including two test methodologies that will become indispensable: cell-aware automatic test pattern generation (ATPG) and hybrid ATPG/logic built-in self test (BIST).
Because semiconductor devices continue to expand in size and complexity, we have to apply more and more tests to ensure detection of all defects. Without the ability to detect all defects, achieving mandated automotive quality levels falls somewhere between difficult and impossible. The increasing number of tests also drives costs higher. To meet quality and control cost, makers of automotive electronics are adopting more efficient test-generation solutions. The most popular approach to minimizing logic test costs today is through the use of ATPG compression solutions. The volume of data the testers need to store and apply is greatly reduced with this approach. Compression alone, however, is proving insufficient. You must also generate patterns more intelligently to maximize the defect coverage of each pattern used.
One way to do this is to use the recently developed approach called cell-aware ATPG. Cell-aware test provides significant defect coverage improvements over traditional ATPG with minimal test cost increase. The cell-aware ATPG approach is based on extracting and modeling transistor-level defects from each cell in a technology library (see Figure 1). These abstracted defect models are then used during the regular test pattern generation process. Many of these defects, especially those in the more complex library cells, go undetected when using test patterns generated using traditional fault models. Silicon experiments have demonstrated the advantages of using cell-aware ATPG. Results from several real-world designs across multiple technology nodes have shown double and triple digit DPM (defect-per-million) decreases over existing test patterns.
Figure 1: The cell-aware ATPG approach is based on extracting and modeling transistor-level defects from each cell in a technology library.
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David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.