At the beginning of this decade, in early 2000, few disruptive technologies had been proposed to replace the industry standard NVM technology and to enlarge the flash application base. A widely accepted statement was that if any technology will succeed, it will materialize in the next decade. As the end of this decade is approaching it can be noted that only one of the proposed technologies is demonstrating the capability to enter the broad NVM market and to be a mainstream memory for the next decade: the phase-change memory technology.
Figure 2 reports the PCM technology development during the last decade. A 180-nm technology has been used to develop the first demonstrator vehicles and to prove the technology viability . Since the chalcogenide material acts as a variable resistor, the PCM cell architecture requires a selector to be coupled with the storage element. Considering the front-end integration, the selector can be either an MOOS transistor or a vertical p-n-p structure, where one p-region will be the substrate or common ground. Consequently, depending on the doping profile of the two junctions the p-n-p structure can be optimized as a bipolar junction transistor (BJTT), exploiting the bipolar action, or as a pure diode. Since, dealing with a p-n-p junction, the difference between the bipolar transistor and diode is very questionable, the acronym “BBJT” can simply represent both.
Click image to enlarge.
Figure 2: PCM technology development over the last decade.
In order to validate the PCM cell architecture, both the BJT/diode-based selector and the MOS-based selector have been integrated in an 180-nm CMOS technology. The BJT-selected cell has been chosen for the high performance and high density applications, since the cell size can be approximately 5F2
(where F is the minimum cell half-pitch). The MOS-selected cell is suitable for system on a chip or embedded applications, because in spite of the larger cell size (approximately 20F2
) the memory integration adds only very few masks to the logic process with a clear cost advantage. A 90-nm technology node has been developed using a 128-Mb product, so-called Alverstone, which is now commercialized. The technology was based on a BJT-selected cell with a cell size of 0.096 µm2
This dimension was obtained using one base-contact every emitter. This cell layout, that gives a larger cell size, has had the advantage to focus all the development efforts on the integration of a very effective and reliable chalcogenide-based storage element, relaxing the constraints on the BJT integration. Having a working and reliable storage element, a more effective cell can be obtained using one base contact every four emitters. This approach has been adopted on the 45-nm technology to achieve a cell size of 5.5F2
 and to design a 1-Gb PCM product . In particular an innovative double STI approach has been adopted as the array isolation scheme: a first deeper STI, with a depth of 270-nm between adjacent WL (x-direction) and a second shallower STI to separate adjacent emitters and the base contact (y-direction). Emitter and base contact resistance has been carefully optimized keeping both active areas salicided. A specific thin CoSi2
layer has been developed to preserve the properties of the base-emitter junction (figure 3).
Figure 3: Lay-out and SEM top-view of the active areas in the cell array.