Figure 2 illustrates the methodology. The dotted red lines are the optimum detection levels shown at any point in “drift” time as they would be positioned with respect to the four resistance level distributions. The distributions would also be the values of the metric “M” where for “read” the technique is to measure the number of clock cycles required for a capacitor, charged by constant current through the cell resistance to reach a given level of charge, the detection level.
Figure 2: Extracting data from cells subject to drift.
The purple lines in figure 2 are representative of the small number of samples of resistance or the read metric obtained from which an estimate of the position of the full distribution, and more importantly its 3 sigma width must be made. The final step is then positioning of the detection levels.
In response to my questions, Dr. Haris Pozidis, Manager of Memory and Probe Technologies at IBM Research – Zurich, offered the following helpful clarification, especially in relation to the two separate aspects of the DLA methodology. “We'd like to clarify that the proposed detection-level adaptation technique is independent of the modulation coding technique,” he said. “Detection-level adaptation works with any data read from the chip, be it uncoded or coded. In other words, the extra information (non-user) added by the possible use of coding is not required, neither used by the detection-level adaptation technique to adapt the detection levels. However, the possible use of modulation coding, in conjunction with the detection-level adaptation technique, leads to improved raw bit error rate performance over time compared to the case of uncoded data with detection-level adaptation. Regarding the term ‘codeword,’ it is indeed used to mean user data with other data added, i.e., in the conventional way.”
He went on to add by way of further clarification, “Our signal-processing framework does not predict the optimum detection thresholds at a later time from the initial relative positions of those detection thresholds at some prior time. Furthermore, there is no need for the user to set the initial values of the detection levels. Instead, the detection levels are automatically calculated at each time instance by the algorithm itself. Specifically, every time a chunk of data is read, irrespective of when these data were written, the algorithm estimates the detection levels that should be used to detect the data. This is a process that is self-adaptive, and only depends on the chunk of data being read, and is independent of any time information. Therefore, the detection levels at any time t
and also t
, would be calculated by the algorithm based only on the data read at that time, and no other information.”
The new lifetime endurance results
The new results for the drift-tolerant technique focused on extended write/erase lifetime operation. The key to this was the evidence that at room temperature the IBM memory cells used could be cycled in excess of 107
cycles before any evidence of wear out started to become evident.
The experimental method was to cycle a block of 64 kcells multilevel cells using just a set/reset pulse, (i.e., the 00 and 11) data states and after a required number of logarithmically increasing cycles write the cells to all four resistance levels for (00,01,10,11), and then at intervals read back the data as a means of exploring drift and the effectiveness of the adaptive level detection system.
The reported results showed that after 106
write erase cycles, the drift correction technique remained more effective than an array operated with fixed level detection thresholds. Error rates at 103
seconds after last programming step ranged from 1 × 10-4
to 2 × 10-4
In a paper presented in 2011  by IBM workers that introduced the MLC-DLA technique, the authors claimed for a block of 200 kcells, “raw” error rates of 10-5
after 37 days (approximately 3.1 × 106
s) after last write. It is assumed that the write/erase lifetimes were for devices that had not been subjected to many write/erase cycles. While IBM claim a more robust cell accounts for the new results, one interpretation could be that the degradation of error rate from 2011 to 2013 could be an illustration of the effect of write/erase wear out mechanisms.
One possible criticism of the experimental method is that iterative programming to obtain the different resistance states involves an initial reset followed by the iterations that involve both crystallization and melting. It could be argued that 106 write erase cycles would be representative of something less if the write erase lifetime cycling involved stepping though all cell resistance levels.
In Part 2 of this article, as well as discussing scaling and the future prospects for PCM, the author will offer some interesting "good news-bad news" speculation on what IBM might report when they complete the elevated temperature stress testing of their DLA-MLCs.
1. H Pozidis, et al., "Reliable MLC data Storage and retention in Phase-Change Memory After Endurance Cycling," Proc NV International Memory Workshop 2013; Monterey, CA (2013).
2. N Papendreour, et al., "Drift-tolerant Multilevel Phase-Change Memory," Proc NV International Memory Workshop 2011.
3. R. Neale, “PCM data retention and the impact of crystal electrodes (Part 2)
,” Memory Designline (2012).