LONDON – Foundry United Microelectronics Corp. (Hsinchu, Taiwan) has taped out a first process qualification chip for its 14-nm FinFET manufacturing process with support from Synopsys Inc. (Mountain View, Calif.).
The test chip is an essential first step in calibrating the manufacturing process and generating the IP cores that will be used to design in that process. UMC has previously said it intends to be in production with the 14-nm FinFET process in the second half of 2014.
In recent years UMC has fallen back in the rankings of foundries as such companies as Globalfoundries, Samsung and Intel have entered into competition with market leader Taiwan Semiconductor Manufacturing Co. Ltd. UMC was behind market leader TSMC in offering 28-nm CMOS with high-K metal gate but has entered into an agreement to collaborate on development 14- and 10-nm FinFET process technology with the IBM Technology Development Alliances group.
EDA support is also necessary to allow engineers to design ICs in a timely manner. The test chip was designed using Synopsys' DesignWare logic IP cores and StarRC parasitic extraction software, a part of the Galaxy design flow.
"We selected Synopsys for this important collaboration based on their FinFET experience and expertise as well as their track record of developing high-quality DesignWare IP in the most advanced nodes," said, Arthur Kuo, UMC vice president of corporate marketing, in statement.
The StarRC parasitic extraction tool uses 3-D modeling to model parasitic capacitance and resistance values which enable 14-nm IP developers to optimize their designs for maximum performance and lowest power. The Galaxy design flow is also described as being "FinFET-ready."
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