Supercaps have many advantages; however, when used in a stack of two or more caps in series, they present the designer with problems such as cell balancing, cell overvoltage damage while charging, excessive current draw and a large footprint/solution. Higher charging current may be required if frequent bursts of high peak power are needed. In addition, many of the charging sources may be current limited, for example, in a battery buffer application or in a USB / PCCARD environment. Being able to deal with these conditions is crucial for space-constrained, higher power portable electronic devices.
Reverse conduction through an IC typically results in a catastrophic event. External fixes such as series rectifying diodes are not very efficient due to high voltage drop. Schottky diodes have less forward drop and therefore higher system efficiency but are more costly than regular diodes. On the other hand, field effect transistors (FETs) offer low on resistances and minimal loss. An internal FET-controlling PowerPath circuit is an elegant way to solve the problem thereby eliminating the potentially damaging consequences. With PowerPath control, in the event the input suddenly drops below the output, the IC’s controller quickly turns the internal FET completely off to prevent any reverse conduction from the output back to the input supply.
Cell balancing series-connected supercapacitors ensures that the voltage across each cell is approximately equal; whereas a lack of cell balancing in a supercap may lead to overvoltage damage. For low-current applications, a charge pump with external circuitry with one balancing resistor per cell is an inexpensive solution to the problem; the balancing resistor value will depend primarily on the capacitor leakage currents as explained below. In order to limit the impact of the current drain due to balancing resistors on supercap energy storage, designers can alternatively use a very low current active balance circuit. Another source of cell mismatch is differences in leakage current. Leakage current in the capacitor cells starts off quite high and then decays to lower values over time. But if the leakage is mismatched between series cells, the cells may become over-voltaged upon recharge unless the designer selects balance resistors that provide significantly more load current on each cap than the cap leakage itself. However, balancing resistors burden the application circuit with unwanted components and permanent discharge current. They also provide no overvoltage protection for each cell if mismatched capacitors are charged at high currents.
For low to medium power applications, another inexpensive (but complicated) approach to solving the supercap charging problem involves using a current limited switch plus discretes and external passive components. In this approach, the current limited switch provides the charge current and limiting, while voltage reference and comparator ICs provide the voltage clamping, and finally an op amp (sink/source) with balance resistors enables supercap cell balancing. Nevertheless, the lower the ballast resistor value, the higher the quiescent current and the shorter the battery run time; the obvious benefit being saved cost. However, this solution is very cumbersome to implement and performance is marginal at best.
Any solution to efficiently satisfy the low to medium current supercap charger IC design constraints outlined above would combine a charge pump-based charger for 2 series supercaps with automatic cell balancing and voltage clamping. Linear Technology has developed a simple, yet sophisticated, monolithic supercap charger IC for these applications which does not need an inductor, eliminates the need for balance resistors, provides reverse blocking, has multiple operating modes and also features low quiescent current.
A simple solution
The LTC3226 is the newest offering in Linear Technology’s family of 2-cell supercapacitor chargers. It is an inductorless supercapacitor charger with backup PowerPath controller for Li-Ion or other low-voltage system rails in applications that require short term backup power. The device employs a low-noise dual mode (1x/2x) charge pump architecture with constant input current to charge two supercapacitors in series from a 2.5V to 5.5V input supply to a programmable capacitor charge voltage between 2.5V and 5.3V. Charger input current is resistor-programmable up to 315mA. The device’s automatic cell balancing and voltage clamping features maintain equal voltages on both cells without requiring balancing resistors. This protects each supercapacitor from overvoltage damage that could otherwise be caused by mismatches in cell capacitance or leakage, while minimizing current drain on the capacitors.
The LTC3226 has two modes of operation: normal and backup. Operating mode is determined by a programmable power fail (PFI) comparator. In normal mode (PFI high), power flows from VIN to VOUT through a low loss external FET ideal diode, and the charge pump stays on to top off the supercapacitor stack. In backup mode (PFI low), the charge pump is turned off and the internal LDO is turned on to supply the VOUT load current from the stored supercapacitor charge while the external ideal diode prevents reverse current flow into VIN. Up to 2A of backup current may be provided from the supercapacitor through the internal LDO.
The LTC3226 operates with a very low 55µA quiescent current when the output voltage is in regulation. The basic charging circuit requires few external components and takes up little space; the IC is offered in a tiny 3mm x 3mm QFN package. The device’s high 900kHz operating frequency reduces the size of external components. Internal current limit and thermal shutdown circuitry allows the device to survive a continuous short-circuit from the PROG, VOUT or CPO pins to ground. Other features include CAP PGOOD and VIN PFO\ (power fail) outputs as well as a VOUT RST\ output for system housekeeping.
The LTC3226 is housed in a compact 16-lead, low-profile (0.75mm) 3mm x 3mm QFN package, with operation from -40°C to 125°C.
Figure 1: LTC3226 block diagram/application
To construct a comparable solution to the LTC3226 requires a convoluted combination of multiple ICs: a buck/boost regulator for SCAP charging, a 2A LDO for backup powerpath, a quad comparator and back-to-back FETs for the external “ideal diode” plus monitoring, and an op amp and various discretes for protection shunts and low-current balancing. Alternatively the user could opt for a “cheap” approach that only charges the SCAPs and provides backup control (without 2 comparators and the op amp); however, there will be no charge current limiting, low-current balancing, cap protection or voltage monitoring features. Compared to more expensive discrete solutions, the cheap method would replace the more expensive high value resistor and op amp combination with inexpensive, low-value resistors that consume a lot of quiescent current and provide no overvoltage protection (clamping) of the supercaps.