Advanced Micro Devices, Altera, IBM, Intel, Sony and Texas Instruments have all introduced 90-nanometer logic devices over the past year. Of those companies, AMD, Intel and IBM have relied solely on internal manufacturing capabilities. The others chose to outsource at least some of their manufacturing to a foundry (Altera to TSMC, Sony to Toshiba and TI to UMC). As with every successful node, the goal of 90-nm process development is to reduce size and costs while improving performance.
While Semiconductor Insights (SI) has analyzed every 90-nm process that is currently commercially available, this teardown provides a focused analysis of the Intel Pentium 4 Prescott processor and the TI TMS320C6416 DSP. Though the chips were designed for different markets, with Intel focusing on high performance and TI on low operating power, a side-by-side comparison is helpful for an understanding of the entire 90-nm node spectrum.
Specifically, we will discuss the definition of the 90-nm node; key performance metrics, such as current drive, power consumption, transistor design and SRAM size; and the wafer cost, from both a wafer and a yield standpoint.
Defining the 90-nm node
The definition of 90 nm remains somewhat open to interpretation within the semiconductor industry. When process node definitions were reliant on DRAM technology, determining process technology was relatively straightforward, since the memory cell size was a simple multiple of the technology measure. DRAM suppliers needed to achieve a specific half-pitch, 90 nm in this case, to meet a process technology. With microprocessors and ASICs, however, it is much more difficult to make a process determination, since many other measurements are taken into account. According to the 2004 International Technology Roadmap for Semiconductors (ITRS), those measurements include MPU/ASIC M1 half-pitch (107 nm), MPU printed gate length (53 nm) and MPU physical gate length (37 nm).
From those measurements, it's clear that gate lengths are typically below the process node value. The reason is that the critical parameter for high-performance logic is the intrinsic gate delay product, which affects the amount of time it takes to charge a CMOS gate (T = C gate x Vdd / Ion, sat). According to the road map, the time should decrease by 17 percent per year. Since 1998, when the 0.25-micron process entered production, that expectation has required the gate length to shrink at a faster rate than the technology node.
A further distinction among the different logic devices claiming a certain process node is application. High-performance devices for desktop applications are designed for complex functions, high performance and high power. The most important performance characteristic for devices attempting to achieve high operating speeds is current drive. Although the switching speed of the device also plays a role, it is the ability of one transistor to drive sufficient charge onto another transistor that limits the speed of most logic circuits. These devices also allow for heat sinks on the package and are allowed a maximum power dissipation of 158 watts.
For their part, low-operating-power devices such as laptops have a medium current drive and medium power dissipation. These tend to lag behind the gate length by about two years and have a maximum power dissipation of 84 W.
Alternatively, low-standby-power components used in battery-powered systems, such as cellular telephones and PDAs, have the lowest current drive and performance but also the lowest power dissipation. These devices are typically three years behind the gate length and have a maximum power dissipation of 2.2 W.
With the advances in technology, the functionality of devices continues to increase, raising the overall complexity. Not only is the process being reduced in scale, but new materials (such as nickel and low-k dielectrics) and new ideas (such as strained silicon, silicon-on-insulator and strained SOI) are also being introduced. Combined, these factors make device testing considerably more difficult, requiring continual investment in test equipment.
Direct measurements, taken from transistor probing, are key to determining the factors necessary to develop a competitive device, since looking at images can only provide information on manufacturing process differences. With transistor probing analysis, we are able to determine the linear threshold voltage, transfer characteristic shift, saturation threshold voltage, subthreshold voltage, body effect, transconductance, current drive, leakage current, punch-through voltage and process gain factors on both the NMOS and PMOS transistors, thereby providing a complete view of the device.
Current drive is perhaps the most important characteristic for high-performance, high-speed logic devices. Although the switching speed of the device also plays a role, it is the ability of one transistor to drive sufficient charge onto the gate of another transistor that limits the speed of most logic circuits. For current drive, Intel leads the market by using a shorter gate length. But there are limits to the heat that an IC can reasonably dissipate, which leads to device leakage and power dissipation. Intel delivers very well in terms of speed, but the device leakage and power dissipation are considerably higher than that of the TI DSP.
Our analysis showed that the TI device is not as capable of delivering current drive over 1 milliamp. The Intel device can drive 1.4 mA for every micrometer of n-channel width, or 40 percent more current than TI's device when looking at the maximum gate bias. At lower gate-drive voltages, however, the two devices are closer in current-drive performance.
Another criterion for 90-nm process technology is power consumption. Portable devices operate on batteries, so minimizing power consumption is key. TI has adopted a strategy to provide high-performing transistors while reducing the number of clock cycles to conserve power efficiency. For all-around performance, combining speed with efficiency, the ratio of drive current to leakage provides the most useful test. In this regard, TI outperforms Intel, with on/off ratios 34 times higher for n-channel transistors and 21 times higher for p-channel transistors.
While the Intel processor is not strictly designed for mobile applications, the increased power consumption is still an issue, since it creates extra heat in the rest of the system. Intel has released a mobile microprocessor, called Dothan, based on the Pentium 4 process we have analyzed, and that part appears to improve on the Prescott's power performance, showing significant decreases in power leakage. Basic structural differences between the processors are negligible.
The measured transistor lengths for the teardown devices, meanwhile, are 45 nm for Intel and 60 nm for TI. The difference occurs because the Intel device is optimized to provide a higher operating speed, providing a higher current-drive performance. The TI DSP, in contrast, was designed for mobile applications, where high operating speed is not as critical.
The two also have different SRAM cell sizes. Both of the devices use a 6T-SRAM, but the TI DSP has a cell size of 0.65 micron x 1.50 micron (0.975 micron2), compared with Intel's 0.90 micron x 1.28 micron (1.15 micron2). Out of all the 90-nm devices SI has analyzed to date, TI's has been measured to have the smallest SRAM cell size.
Wafer cost-and yield
The final issue to consider is manufacturing cost, from both a finished-wafer and a yield perspective. Using 90-nm process technology requires more efficient design and process techniques, but those advancements can increase cost because they require more expensive materials and reduce wafer yield.
As the world's largest semiconductor company, Intel really demonstrates its manufacturing capabilities here. Despite the complexity that results from adding germanium into the p-channel source and drains of the Intel processor, the cost of the finished Intel wafer is approximately 12 percent lower than that of the finished TI wafer, SI estimates.
Cost per wafer is only one part of the cost equation: To obtain a full view of the wafer cost, wafer yield must be taken into account. It is more difficult, however, to determine an accurate estimate of the wafer yield for each manufacturing line. Through a very detailed analysis of both structures, SI has determined that the Intel devices are most likely very sensitive to slight mask misalignments. During the course of a comprehensive construction analysis of the Intel processor that generated several hundred SEM and TEM images, not even slight layer misalignments were found.
Of course, mask misalignments will always be present to some degree; this is certainly evident in other 90-nm devices we have analyzed. The fact that every transistor contact was perfectly aligned in the Intel device tells us that the yield was highly sensitive to slight alignment problems and that wafers with chips exhibiting such problems failed wafer test. Such sensitivity will reduce the wafer yield considerably below the wafer yield achieved by TI.
When considering both of these issues, TI DSPs are likely less expensive to produce than Intel processors.
The most interesting facets of process design are the gate stack and substrate engineering. Intel uses a more advanced, and more expensive, process that strains both the n- and p-channels. This provides performance benefits, since the p-channel transistors are optimized separately from the n-channel transistors. The technique employed required the Intel process team to make a switch to nickel for the gate and contact metal salicide at an earlier node than expected. TI continues to use a cobalt-salicide process held over from the 130-nm node.
The mobility-enhancement techniques used for each device also differ. The Prescott's NFET performance is enhanced essentially through process-induced strain with a nitride film deposition following the gate stack.
Hole mobility for the PFETs depends on a complex selective epitaxy that deposits silicon germanium into the source and drain regions. It is the use of germanium that required the shift to nickel for the salicides.
TI approaches mobility from an entirely different direction. Wafer orientation is shifted from the usual < 100 > direction by 45 degrees to < 111 >, thereby enhancing p-channel performance. This creates its own issues: TI may have encountered dicing problems because the angle shift puts die edges off the cleave plane. TI appears to be keeping the scribe channel as clear as possible to avoid cracking. Although it is not possible to give a "before and after" view of this enhancement technique, it does provide TI with an increase in current drive.
There are other structural differences between the devices. The thinner Intel dielectric reduces threshold voltage by approximately 15 percent. The shorter gate length provides more edge in current drive.
-Don Scansen (email@example.com), technology manager for processes at Semiconductor Insights (Ottawa).