Charged-coupled devices were the first solid-state image sensors. CCDs offer superior picture resolution, but because they require more power, they are generally more expensive to create than CMOS image sensors. While the latter have generally lagged CCDs in terms of image quality, they have been able to compete in the imaging market by taking advantage of standard CMOS process technology. This results in a smaller form factor, reduced weight and lower cost, making CMOS sensors ideal for high-volume consumer and mobile applications.
Traditionally, the CMOS vs. CCD battle has been a trade-off between image quality and image quantity. CCD image sensors have delivered superior quality, while CMOS image sensors have provided better performance in terms of battery life as well lower cost. As a result, CMOS sensors have been shipping in higher volumes.
But the traditional boundaries are blurring. CMOS image sensors increasingly are rivaling the image quality that CCDs have traditionally provided. They are able to accomplish this by improving the surface preparation of the silicon in the photodiode region, which results in better noise performance. To compete in the high-volume marketplace, meanwhile, CCDs have responded by employing new methods to reduce their cost structure.
This article will briefly highlight the major differences between these competing image sensor technologies and discuss their battle for market dominance. It will compare a 3-megapixel CMOS image sensor from Micron Technology Inc. with a Panasonic Corp. 4-megapixel CCD image sensor, used in the Panasonic DMC-FZ10 digital camera. Special emphasis will be placed on the innovations evident in the Micron design.
CMOS and CCD image sensors work on the same general principle. Simply put, when an image is taken, the sensor records the amount of light entering a specific pixel. This information is converted into a digital format, stored and read back so that the image can be viewed.
The main difference between these technologies is the method used to store the image data. CCDs store charges across the chip and start reading back from one corner of the array. This provides a very detailed image, but the method is slow unless a significant amount of die area is occupied, thus increasing the cost. CMOS uses an active-pixel sensor with several transistors in each pixel to facilitate amplification and readout. The amount of usable die area is reduced when data is read at every pixel, but the CMOS device can convert the data much faster than a comparable CCD sensor.
The average user of a digital-imaging device expects a 3- to 5-megapixel quality range, an affordable price point and a small form factor. This pixel count permits an 11 x 17-inch picture to be printed and allows for some afterimage modifications, such as cropping or zooming, without distorting the photo. A reasonable price point opens the door to the average consumer. The small form factor, including lighter weight, means that the imaging device will be available when needed without prohibiting range of motion.
When digital cameras were standalone products, image quality, or megapixel count, was the primary purchase criterion. Consumers wanted the largest megapixel number they could get for a given price. As the convergence between cameras and handsets continues to accelerate, the primary purchase criteria become cost, form factor and power consumption, with image quality becoming a secondary factor. While image quality is still considered in the purchase of a handset, a high megapixel range, likely beyond 6 megapixels, will not be commercially viable in today's handsets.
Delivering a 6-Mpixel-or-greater image sensor would require extra image processing, memory space and manual feature control-requirements that collectively would price the handset out of reach for consumers. This ceiling makes it more likely that CMOS image sensors will be able to succeed in the handset market: Anything beyond 6 megapixels would be more for bragging rights than for true necessity.
System view shows that Micron's MT9T0001 CMOS image sensor (left) yields a smaller system die size than Panasonic's CCD because the CMOS chip integrates the imager, A/D converter and digital image processor.
Both Micron and Panasonic are experienced in high-volume markets, but each chose to invest in a different image sensor technology. Micron is able to apply its DRAM volume-manufacturing expertise to CMOS image sensors. Panasonic is also an experienced high-volume CCD player.
From a system perspective, Micron's MT9T001 is a camera-on-chip. This is the reason for the considerable die-size discrepancy between the two image sensors. In a typical imaging system, there are three main devices that are needed to take a picture: an imager, an analog-to-digital converter and a digital image processor. With CMOS devices, you can integrate all those functions on a single chip. While the Micron chip is larger than the Panasonic CCD image sensor, when all three of the necessary components are added to create a full CCD system, the total CMOS system size is smaller. The converged functionality also lends itself to more streamlined designs and lower power consumption.
The optical format measurements for the two devices are essentially the same, showing that CMOS is capable of competing in terms of the size of its active chip area. The larger optical-format size requires a larger chip die to accept light for taking an image. As technology advances, smaller optical formats can be used that still provide the desired picture quality.
The final consideration is the pixel size. To form an image, each pixel captures the entering light. Larger pixels allow more light to enter. This enables a more vibrant image but also requires a larger die. A larger optical format also calls for the use of a higher-quality, more expensive lens.
Traditionally, an active-pixel CMOS image sensor requires a minimum of three transistors for each pixel. Most chips on the market use a four-transistor pixel. Micron, however, has developed an innovative way of sharing the readout circuitry between two pixel elements, putting the effective number of transistors per pixel at 2.5. This is the direction in which CMOS research has been moving with Sony, Canon and Maicovicon, which have all announced consistently lower transistor counts.
See Figure: Pixel size comparison of CMOS (top) and CCD sensor shows that Micron Technology has shrunk the effective number of transistors per pixel from 3 to 2.5.
Using this technique, Micron is able to shrink its image sensor while providing quality comparable to CCD technology.
This advancement also drastically increases the fill factor found in a Micron pixel. By moving the transistors out of the pixel area so that they can be shared between adjacent pixels, the space available for light to enter the image sensor, or fill factor, is greatly increased. Most CMOS image sensors analyzed have a fill factor range of around 30 percent. The changes made by Micron, however, have allowed for a 60 percent fill factor.
In fact, the light-capture area of the Micron sensor is five times larger, at 5 micron2, than the Panasonic CCD, at 1.2 micron2, though the CCD pixel size is much smaller. Although an improved CMOS process still suffers from more noise sources at the pixel than a CCD, even its detractors admit that capturing five times as many photons as the competition lets CMOS imagers close a big part of the image-quality gap.
From a process standpoint, the distinguishing feature of the Micron MT9T001 is the double-poly process. The process allows the company to integrate one capacitor per pixel pair into the active-pixel sensor layout.
The two-poly process puts an extra capacitor into the circuit, increasing the capacitance at the "hold" node of the circuit. This improves the performance by reducing the effect of clock noise and leakage current on the efficiency of the source follower circuit. The added poly level and mask cost Micron a mask step, but its DRAM fabs are experienced in providing up to five poly deposition steps under severe price pressure.
- Don Scansen (email@example.com), practicing engineer, technology manager for processes at Semiconductor Insights Inc. (Kanata, Ontario.).
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