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The commodity DRAM industry is ruthlessly competitive, with razor-thin margins, relentless downward pressure on prices and billion-dollar bets on new fabrication facilities. Membership in the industry is now limited to an elite few that have mastered high-volume, commodity production. The list includes Samsung, Micron, Qimonda (previously Infineon), Hynix and Elpida.
In an industry as competitive as DRAM, risk taking and revolutionary technology changes are not encouraged. For instance, it was only at the 1-Mbit generation, years after the rest of the semiconductor industry, that DRAM makers finally switched from NMOS processing and circuitry to the higher-performance, but more costly and complicated, CMOS.
The DRAM industry has taken a pass on some other process changes that have become mainstream for other semiconductors, including the use of epitaxially grown substrates, silicon-on-insulator (SOI) and metal interconnect systems for anything more than three levels. Until recently, copper metallization would have been included in the list of advanced technologies that failed to find a foothold in the DRAM world, but no longer. Micron Technology Inc. has become the first DRAM vendor to produce commodity DRAM with copper, rather than traditional aluminum, interconnect.
Aluminum 6F2 110-nm process.
Copper metallization was introduced into commercial production by IBM on its PowerPC microprocessor in 1998. The change to copper was motivated by the increasing difficulties of scaling aluminum metallization chiefly the parasitic interconnect resistance and associated interconnect delays. Copper's lower resistivity and far greater electromigration resistance made it the ideal material.
Significant process changes were required to implement copper, however, primarily because of the lack of any reliable copper dry-etch technology. Changes included completely new deposition and patterning technologies (electroplating and damascene).
Copper 6F2 110-nm process.
IBM's introduction of copper was a revolutionary change, but the rest of the industry slowly followed. Advanced Micro Devices produced a 180-nanometer, six-level-metal version of its Athlon in 2000, and Intel Corp. made the switch in 2002, producing a 130-nm copper Pentium 4.
IBM's copper fuse.
Adoption of copper spread to the rest of the industry, including the foundries. Today, virtually all production at 90 nm or below is in copper, except for commodity memory.
The potential benefits of copper for DRAM are fairly straightforward. Because of its lower resistivity compared with aluminum, it can be used in the cell array to shrink the height of the minimum pitch metal lines, easing the problem of dielectric gap fill and decreasing the parasitic bitline-to-bitline capacitance and noise coupling. In the periphery, copper allows longer wiring runs and can support new, high-speed DRAM architectures such as DDR3 or DDR4.
For a number of reasons, though, the DRAM industry has avoided copper in favor of tried-and-true aluminum technology. One fundamental reason has been cost. Introducing copper in the early days of the process would have required costly investment in new (and at the time potentially unreliable) back-end technology, including electrochemical plating tools and patterning by the additive dual-damascene process.
The greatest hurdle, however, has been contamination. Copper is an infamous element among silicon fab engineers because it can degrade critical device parameters, such as gate oxide integrity and junction leakage. Junction leakage is of much greater concern for DRAM than for logic, because information is stored in the DRAM as a charge on the cell capacitor. The leakage through the cell access transistor must be minimized to maintain the integrity of the data stored and prevent unacceptably high refresh rates.
Copper ions are notoriously mobile in the oxide isolation traditionally used to insulate metal layers. Thus, to be viable for DRAM, any copper metallization process must employ a bulletproof barrier material around the copper to prevent migration to the substrate.
The good news is that over the past eight years, the semiconductor industry has created a whole series of barrier processes and materials to confine copper metallization and prevent contamination.
It should be noted that copper metallization has been successfully used with embedded DRAM for some time. In a device for the Xbox360 gaming unit, NEC integrated embedded DRAM using stacked MIM capacitors in a seven-level copper logic process. IBM has manufactured several eDRAM devices with advanced copper logic back-end processes.
Rumors of the advent of copper for commodity DRAM metallization have circulated in the industry for some time, and Semiconductor Insights (SI) has now identified copper metallization devices in volume production at major DRAM maker Micron Technology.
In the world of DRAM, Micron is the No. 2 player, behind Samsung, and is the recognized cost leader. To achieve cost leadership, Micron has continually innovated, blazing an independent technology path rather than following the herd. The company has a track record of introducing radically new technologies to reduce cost.
In the 1990s, when IBM was using a process that required close to 30 mask steps to produce its trench capacitor-based DRAM, Micron was producing devices using a streamlined, 15-mask-step process. Anther de- parture from the mainstream was Micron's use of electrical antifuses rather than traditional laser fuses to swap out failing rows or columns for good ones. Antifuses are an economical alternative, since they consume less silicon area and do not require expensive lasers.
Perhaps the best example of Micron's willingness to make big bets was its introduction of a 6F2 cell design in 2004 ("F" being the minimum feature size of the device). That rollout date beat the International Technology Roadmap for Semiconductors prediction by four years and marked a theoretical 25 percent area reduction over the conventional, 8F2 cell.
Now Micron has brought copper interconnect to a DRAM chip. The device we examined, the MT47H32M16CC-5E, is a 512-Mbit DDR2 built at the 110-nm node. Layout and circuitry appear identical to an aluminum version previously analyzed. This indicates that Micron's circuit designers took prudent steps to test the copper process on a proven production design to validate the solution before attempting to take advantage of the speed advantages available with copper.
Compared with the aluminum version, the copper-based device achieves a reduction in the height and aspect ratio of the metal lines. The height of the metal-two wordline straps has been reduced by 50 percent. The metal-one layer height was cut by 25 percent.
Despite some minor flaws in the wiring, Micron appears to have solved the copper integration issues for global DRAM interconnects.
Switching to copper usually adds wire-bonding complexity. Most copper devices have an aluminum metal patterned only on the pad areas, expressly to allow standard gold wire bonding. That adds cost, in the form of a further deposition and additional mask and etch steps. Micron's innovate bond pad design avoids the cost adders. It allows the same die-finishing process to be used for parts intended for system-in-package integration as for those headed for single-die packaging. Creating a line of 512-Mbit chips that way may give Micron a cost edge to gain design wins in new areas.
Micron's transition to copper has also been eased by a unique antifuse redundancy scheme that is based on using the capacitor cell dielectric. A high voltage ruptures the dielectric to create a permanent connection and replace a failing row or column with a redundant one.
All other manufacturers use metal fuses blown by laser, and any change to copper interconnect would require reengineering of the fuse scheme. For Micron Technology, however, that is not a consideration.
Micron's use of copper has been presaged by its patenting program. You may not think of Micron when you hear about damascene copper processes, but the company does hold patents in that area.
The DRAM industry appears poised for a significant, and potentially disruptive, materials and process technology transition to copper interconnect.