The Omap2420 is produced using a seven-metal, single-poly, 90-nm CMOS (copper) process; the die measures 144 mm2 (12 x 12 mm). All of the digital blocks were designed using a standard-cell approach, and the total area used by standard-cell blocks was close to 40 percent of the die size.
Guided by an analyst, SI's proprietary software extracted each unique standard cell. For each cell, length and width measurements were taken.
Next, using a complex searching algorithm in the imaged area, each occurrence of a cell instance was identified. The automated method enabled an accurate determination of the cell density within the target area.
The standard-cell library used in the Omap2420 device comprised 245 unique logic cells, and there were more than 115k logic cells in the imaged area. In some cases, the same function was embodied in a number of standard functional cells differing only in the driving power and layout topology. Nonfunctional or dummy cells were found at the poly/diffusion layer, with the poly in the shape of either simple bars/inverters or capacitors, in order to control process distortions in areas within the standard-cell region where an individual cell could not be placed.
The standard-cell utilization was then calculated by dividing the area of all functional cells by the total area analyzed, resulting in a value of 74 percent. Given that the area of a NAND2 gate with normal drive strength was found to be 3.44 square microns , the raw gate density of the functional area was found to be 394k gates/mm2.
As process nodes move to 90 nm and smaller, other aspects of the cell library should be considered, such as design-for-manufacturability (DFM) and the target application. For instance, multiple-threshold CMOS (MTCMOS) employs low-voltage-threshold devices for speed performance and high-voltage-threshold devices for low-power consumption.
An interesting area for MTCMOS standard-cell analysis is to examine the switching technique that's used to turn the power supply on and off to the low-voltage-threshold, high- speed devices.
Also of interest is the power supply routing in a given power domain--to observe, for example, the use of constantly powered buffers that allow for routing of critical signals through an area regardless of whether the region was powered down.
At the physical-layout level, yields may be increased without enlarging the design area by applying select DFM concepts. Those include increasing contact/via metal overlap, using wider and longer metal end-of-line extensions, and using redundant vias/contacts in order to decrease the likelihood of contact/via failures. In addition, the number of critical features can be reduced by limiting poly and diffusion routing, and using straight transistors.
As more analog functions are performed by digital circuits, the sophistication of the standard-cell blocks becomes critical to SoC performance. IC designers must also closely monitor the competition. They can benchmark their design against the competition by using SI's proprietary software, tools and lab techniques, which extracts the standard-cell library used in a device, and provides an accurate calculation of the standard-cell area utilization and cell density.
Michael Keller (firstname.lastname@example.org) is wireless technology manager at Semiconductor Insights (Kanata, Ont.). He has completed a PhD in quasi-optical millimeter-wave circuits and antennas.