On Nov. 12, Intel shipped the first 45-nanometer microprocessors using high-k metal-gate technology. Whether to underscore the significance of the event or to reinforce that his famous law remains on track, Gordon Moore has become a central figure in the marketing of Intel's 45-nm technology. Moore describes the innovations as "the biggest change in transistor technology since the introduction of polysilicon-gate MOS transistors in the late 1960s." Even Time magazine recognized the Intel Penryn microprocessor as one of the best inventions of 2007.
But there is substance behind the hype. The silicon semiconductor industry is deeply in love with polysilicon. It's just too hard to let go of this workhorse; in fact, many manufacturers won't do so until the 32-nm node. Intel has a reputation for introducing new technology sooner than the rest of the industry, and its 45-nm processor is no exception.
The transistor engineering that Intel has achieved largely, but not exclusively, by incorporating high-k metal gateHkMG, as it is often taggedis a huge leap forward.
Moore's Law proceeds as the size, power and performance of the MOS transistor scale. The physical dimensions of the transistor have been stuck since the 90-nm node. Once gate dielectrics shrank to around 1.2 nm (or approximately four atomic layers), there was nowhere left to go.
Silicon CMOS grew into the ULSI world we occupy today largely because of the native oxide that grows readily on every silicon surface. The ability to grow SiO2 with very low defect densities on the channel surface spawned NMOS and then CMOS that displaced silicon bipolar technology for integrated circuits. Nitrogen incorporation into SiO2 gained a bit of electrical performance starting at the 130-nm node.
Replacement materials for the gate dielectric were expected by 90 nm to maintain the pace of Moore's Law. However, the widespread adoption of channel strain engineering postponed gate dielectric replacement by a few generations. Strained silicon boosted the transistor performance and power consumption to maintain progress without the introduction of revolutionary materials.
Die Markings: Intel Penryn. |
But thinning of oxynitride, or SiON, gate dielectric is at the end of the road. With SiON providing only about a 50 percent improvement in dielectric constant (k), a fundamental shift in materials is necessary. Further thinning of SiON would create unacceptably high gate leakage current and reduce device reliability. The 1-nm-thick layer of SiON, required for 45-nm device targets, is essentially just three atomic layers thick. Not only is leakage a huge problem, but there is no margin left for thickness variation.
The advantage of using a high-dielectric-constant material is that it can be made physically thick, to limit the gate leakage current, while being electrically very thin, to provide adequate control over the FET channel and to maintain or increase performance.
Intel is known for aggressive scaling, especially in the gate dielectric. Physical thickness values at 65 nm were 13 percent thinner than those found on Advanced Micro Devices' quad-core microprocessor. The fundamental difference between Intel and AMD technology at 65 nm was the starting wafer. AMD switched to silicon-on-insulator (SOI); Intel stayed with bulk silicon. This might seem illogical at first, since SOI devices suffer less from gate leakage and could meet specifications with thinner gate dielectric. AMD's approach was to limit power consumption even more for a given level of transistor performance.
NMOS Transistor: SEM Cross Section. |
Intel claims that further reduction of the SiON thickness is feasible but is likely not production-ready or worthy of the effort to make it so, considering the lack of scalability to 32 nm. To illustrate that point, it was put this way at the IBM Common Platform Technology Forum in early November: "Atoms don't scale."
Prior to announcements of 45 nm and high-k, Intel's senior fellow for the Technology and Manufacturing Group, Mark Bohr, often remarked that channel leakage between the source and drain was much more significant than gate-to-channel leakage. Intel's view was that SOI was not worth the effort and added cost. Earlier in the heyday of driving MPU clock frequencies ever higher, transistor guru and fellow Tahir Ghani declared that gate leakage current densities in the neighborhood of 100 A/cm2 would be acceptable (Ref. 1). The consensus target at the time was only 1 A/cm2. Consequently, Intel forced the rest of the industry to relax its expectations of attainable gate leakage.
But that was then. Now we arrive at a new age for integrated circuits. Strange new materials appear for the first time in the gate stack of Intel's 45-nm transistors. With its leap forward in gate stack technology, Intel now targets leakage improvements of 10x or more.
PMOS Transistor: SEM Cross Section. |
High-k dielectrics are not completely new to the industry. Moore's Law has already driven DRAM cell dimensions to a point where specialized dielectrics were required in the storage capacitor.
A variety of materials are in widespread use in DRAM. Al2O5 and ZrO2 are both used in high-volume DRAMs by different vendors. But Intel is the first logic IC manufacturer to implement any type of high-k material and the first anywhere in the industry to produce FETs with a high-k gate dielectric.
Technology road maps
The 2005 International Technology Roadmap for Semiconductors pointed to 2008 for the technology to be available, but more important, it indicated a gate leakage of around 900 A/cm2 as the point at which high-k dielectrics must be introduced.
Two possibilities appear viable for HkMG at 45 nm. You could start with a mid-gap metal and optimize the gate dielectric material separately for the NFET and the PFET. This is the dual high-k approach. The other option is to use a single gate dielectric material while tailoring the choice of gate material for N- and P-type devices. This is known as a dual gate process. The latter option is Intel's choice and likely what analysts have been betting on the longest.
The main features of Intel's 45-nm technology are the use of HfO2 as the high-k dielectric material, TiN for the NFET replacement gate, and TiN barrier alloyed with a work function metal for the PFET replacement gate.
Intel has published an article with what is believed to be its final material choices, but fabricated with conservative design rules (Ref. 2). Intel senior fellow Robert Chau and his co-authors (all of whom are prolific in the Intel HkMG portfolio) claim ION = 1.66 mA/micron for NFETs with IOFF = 37 nA/micron at 1.3-V drain voltage. Claimed PFET figures are ION = 0.71 mA/micron with IOFF = 45 nA/micron.
These values were obtained from 80-nm gate-length transistors. Our characterization of Intel transistors is now complete and ready to compare with data from the literature.
It may seem odd that the introduction of high-k gate dielectrics has not reduced the equivalent oxide thickness (EOT) of Intel's 65-nm SiON. In fact, our measurements and projections suggest a slight increase. The real story here is metal-gate technology, however, so we agree with Moore that this may be the biggest change in transistor technology since the introduction of polysilicon gates. As others have pointed out, it brings the MOS device full circle to the earlier use of metal gates (Ref. 3).
For many generations, the most significant part of the EOT scaling problem was the depletion capacitance of polysilicon gates. Nature would not allow polysilicon to become more metallic to overcome the problem. Physical scaling of the SiON was also at its limit. Intel had to switch to metal gates, and it made good sense to replace oxynitride for the new dielectric at the same time. Going forward, Intel will continue to improve the dielectric process parameters to begin to scale the performance of the new high-k stacks.
It seems feasible for the 45-nm node NFET to break the 2-mA/micron barrier. However, we do not expect to see much performance gain over the 80-nm test structures in this first-generation Intel 45-nm process.
But was Intel first to 45 nm? Perhaps Matsushita/Panasonic's newest process deserved an earlier mention, but I think it has, or will, become accustomed to occupying Intel's 45-nm shadow. In terms of size and transistor density, Panasonic's UniPhier IC achieved a true 45-nm technology and put it into the market earlier than Intel. Panasonic Blu-Ray players with the technology appeared on the market in early November. By implementing immersion lithography, Matsushita/Panasonic has achieved the smallest minimum metal patterning that we have seen to date, at 67-nm M4 half-pitch. However, the gate stack technology is traditional and well behind Intel's. The 36-nm poly gates are not designed for best performance but rather for squeezing two parallel H.264 decoders onto a single piece of silicon.
Perhaps surprisingly, Panasonic achieves tighter metal pitches than Intel. While Intel might be proud of extending dry litho to 45 nm, it cannot match the dimensions from Panasonic's fab, which is running immersion tools now. For example, the UniPhier device displays a minimum pitch of 138 nm up to metal four. Compare that with Penryn's metal-two pitch of 158 nm.
Intel has chosen a solution for 45 nm that will readily scale to 32 nm with only continuous process improvement rather than significant materials changes. Beyond 32 nm, it will be a new ball game. The line widths of sacrificial poly at 22 nm will leave trenches too narrow to deposit metal-gate materials. We can expect Intel to adopt a vertical-channel transistor technology, which it refers to as tri-gate, that will incorporate many of the materials technologies introduced on the 45-nm platform (Ref. 4).
While Intel may have been beaten to 45 nm, its high-k metal-gate stack technology is a significant technological achievement and will allow transistor scaling to restart where it has been stalled for many years.
Don Scansen is semiconductor technology analyst at Semiconductor Insights, a CMP Technology company. He holds a BSEE, MS and PhD degrees from the University of Saskatchewan and was a recipient of the Nortel Industrial Scholarship. Scansen is a licensed professional engineer in the province of Ontario and a senior member of the IEEE.
(1) T. Ghani et al., "Scaling Challenges and Device Design Requirements for High Performance Sub-50nm Gate Length Planar CMOS Transistors," 2000 Symp. on VLSI Tech. Dig. of Technical Papers
(2) Robert Chau et al., "High-k/Metal-Gate Stack and Its MOSFET Characteristics," IEEE Elec. Dev. Lett., June 2004, pp. 408-410
(3) Dick James, "The Wheel Turns Full Circle: Hypothesizing on Intel's process at 45 nm," Chipworks blog. www.chipworks.com/blogs.aspx?id=4422&blogid=86
(4) Kavalieros et al., Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering, 2006 Symp. VLSI Tech. Digest of Technical Papers