As DRAM prices continue to fall and most manufacturers experience financial hardships, only innovation and aggressive scaling will ensure a company's success. Because DRAM device scaling is applied mostly to DRAM cells, array architecture plays the most crucial role in determining chip size.
Traditionally, an 8F2 cell design and a folded bitline array have constituted mainstream DRAM architecture, proving to be the most reliable design in terms of manufacturability and DRAM array operations. Both symmetric array design and the close physical location of bitline pairs help to achieve the most reliable sense-and-restore operations for DRAM cells with folded bitline architectures.
Some DRAM manufacturers, notably Micron and Samsung, have also used a 6F2 cell design, providing about a 25 percent improvement in DRAM cell area. Although a 25 percent reduction in DRAM cell size is promising, some obstacles have arisen to adopting this technology for production. In addition to the process challenges naturally associated with smaller DRAM cells, such a design forces designers to use an open bitline architecture because of its tight pitch for bitline sense amplifiers. Open bitline architectures, however, are considered less immune to array noise.
In an open bitline architecture, each bitline pair comprises two bitlines located on either side of the bitline sense amplifier. In a folded bitline design, a bitline pair has two bitlines physically located next to one another in the same half of the bitline sense amplifier, helping reduce the effect of any array noise, which is applied equally to the pair of bitlines. Folded bitline architecture also provides total use of the DRAM cell array. In an open bitline design, the cell arrays at the edges offer only half the use of those in folded bitline designs.
Micron has been using the 6F2 cell design for many years. Semiconductor Insights has seen Micron's 6F2-based design in its 95-nanometer 512-Mbit DDR2, 78-nm 1-Gbit DDR3, and 78-nm 2-Gbit DDR2 DRAMs. Having recently analyzed Samsung's 80-nm DDR2 device, Semiconductor Insights has noticed that Samsung has also made the transition to 6F2-based design for its Rev. E DRAM. By comparing the designs of Samsung's 6F2 80-nm DDR2 DRAM and its 8F2 90-nm DDR2 device, some insight is possible into the pros, cons and design challenges of 6F2. By comparing Samsung's 6F2-based 80-nm DDR2 design with Hynix's 8F2-based 80-nm DDR2 device, a direct comparison of 6F2-based and 8F2-based designs is possible.
Semiconductor Insights' analysis revealed that adopting the 6F2 techniques forced the Samsung design team to make the new 512-Mbit DDR2 DRAM look very different from the previous-generation design. The array block--a building block having cell array and bitline sense amps--now has 320 wordlines per array block, a reduction from the 90-nm 8F2-based design's 512 wordlines per block. It appears that Samsung reduced the number of cells connected to a bitline to mitigate the effect of array noise and to help sense-and-restore operations in 6F2-based array design.
Samsung also used an unconventional array design. Traditionally, array blocks have provided wordline totals in powers of 2, such as 128 (27), 256 (28) or 512 (29). But the 6F2 design has 320 wordlines (not a power of 2). Samsung seems to have walked a line between reliable operation (by having less than 512 wordlines per bitline) and area efficiency (by having more than 256) to save the number of bitline sense amplifiers.
Samsung stuck with the 8F2 architecture for its 90-nm, 512-Mbit DDR2 DRAM, Rev. C. |
Samsung switched to 6F2 for its 80-nm, 512-Mbit DDR2 DRAM, Rev. E. |
Because of the nature of open bitline architecture, however, the number of bitline sense amplifier blocks in the chip height direction has increased by 68 percent. Row redundancy has been reduced by 20 percent. By transitioning from a 90-nm 8F2-based design to an 80-nm 6F2-based design, Samsung has achieved a 47 percent increase in the number of gross dice per 12-inch wafer.
Although the comparison of the two Samsung devices (Table 1) shows dramatic improvement in terms of number of gross dice per wafer, it is hard to understand the effect of device geometry scaling (90 nm to 80 nm) and cell/array architecture change (8F2 to 6F2).
To analyze the effect of 6F2-based design, Semiconductor Insights analyzed two comparable 80-nm DDR2 designs from Samsung and Hynix (Table 2).
The comparison of cell size between the designs clearly demonstrates the trade-offs of 6F2 DRAM cells: a 24 percent reduction in cell size only. But the impact on chip size (although other factors may affect the chip size as well, assuming the periphery designs are done similarly) is only about half the result enabled by the 6F2 cell design.
The effectiveness of 6F2-cell-based DRAM is reduced by the additional design challenges associated
with an open bitline architecture: underused edge arrays and fewer wordlines per bitline (hence more bitline sense amplifiers). Careful selection of the array block is the key to the optimum design of 6F2-cell-based DRAM products.
The overall gain of 6F2-cell-based designs in gross dice per wafer for a 12-inch production line is estimated to be around 15 percent.
Although the 6F2 cell's advantage of 24 percent less area is mitigated by a die-count increase of only 15 percent more dice per wafer, this increase in the number of gross dice is nevertheless essential to maintaining profitability and competitiveness. n
Young Choi (email@example.com) is memory technology
manager at Semiconductor Insights, a CMP company specializing in in-depth technical investigation of ICs and electronic systems.