As 40-nanometer NAND flash products are prepared for mass production, and as technologies emerge to achieve densities beyond 2 bits per cell (multilevel-cell technology), with 3- and 4-bit/cell technology in sight, reviewing the first four generations of NAND flash technologies can provide a clearer view of the how the industry might evolve over the next few years.
NAND flash, because of its smaller cell size and nonvolatile data storage, has become the storage
device of choice for many consumer electronic devices, especially portable and handheld applications. The driving force behind the ubiquitous application and use of NAND flash devices is the continuous innovation in the process technologies and design techniques used to implement larger NAND flash devices with reduced production cost. This article examines the latest trends in NAND flash process nodes, cell types, chip
sizes and cell sizes from a device technology standpoint.
Fifteen NAND flash devices from five manufacturers (Samsung, Toshiba/SanDisk, Hynix, STMicro, and Intel/Micron) have been analyzed. Detailed structural and circuit analyses of the select devices conducted by Semiconductor Insights are the basis of this article. The analysis focuses on the latest NAND devices, ranging from 2-Gbit single-level cell to (SLC) to 16-Gbit MLC types. All NAND flash devices analyzed in this article are based on floating-gate technology.
The accompanying table lists the NAND flash devices that were examined. The devices are sorted according to process node. (Note that Toshiba/SanDisk's 43-nm NAND flash information is sourced from ISSCC 2008 data.)
The list covers major NAND flash devices introduced from late 2005 to 2008 and covers both SLC and MLC products. Process nodes range from 90 nm for early products in 2- and 4-Gbit densities to the latest, 43-nm products at 16 Gbits.
The latest NAND flash devices commercially available as of January 2008 are manufactured in 50-nm-grade technologies that include 50, 51 and 56 nm. IM Flash Technologies (IMFT, a joint venture of Intel and Micron) is the leader in terms of minimum feature process size, at 50 nm. Toshiba/SanDisk manufactures MLC products in 56-nm process technology with immersion lithography. The minimum feature size of Samsung's latest 16-Gbit MLC NAND flash is 51 nm.
NAND flash densities and process nodes. |
Meanwhile, 50-nm process technologies from Toshiba/SanDisk and Samsung introduced in 2007 have been essential to maintaining competitiveness in a climate of rapidly declining NAND flash prices. In February 2008, Toshiba/SanDisk announced a 16-Gbit MLC NAND flash device manufactured in 43-nm process technology (the most advanced MLC NAND flash device to date).
The previous generations of NAND flash devices range from 60 nm and 65 nm to 70 nm and 73 nm. These technologies were adopted to produce 4- and 8-Gbit SLC/MLC NAND flash devices in 2006 and 2007, and a 90-nm process node was widely used for 2- and 4-Gbit MLC devices between 2004 and 2006.
By means of advanced process technology, NAND flash density has been continuously increased from 2 Gbits at the 90-nm node to 16 Gbits at 43 nm. Despite the increase in density, the chip size of NAND flash devices has ranged from 130 mm2 to 170 mm2 until the 43-nm process node. The latest 16-Gbit MLC NAND flash announced by Toshiba/SanDisk achieved an impressive die size of 120 mm2. That opens the door to 12-inch-wafer processing capabilities for cost-effective manufacture of 32-Gbit MLC NAND.
NAND flash chip size and process nodes. |
NAND flash cell sizes have been continuously reduced as process technologies have advanced. The current, 50-nm process node is close to 0.01 square micrometer, almost 3.5 times smaller than the most advanced DRAM cell size examined by Semiconductor Insights. The simple structure and layout of NAND flash cells (based on a 4F2 cell design) help achieve the smallest possible cell design with whatever process technology is used.
The NAND flash industry has continued to improve lithography to define smaller geometry and achieve smaller cell sizes. Despite some technical challenges, the current 43-nm process technology has achieved 40 percent smaller cell sizes than were achieved using the previous, 56-nm process node.
NAND flash cell sizes, expressed in terms of multiples of minimum feature size square (F2), show the trend. Most of the NAND flash devices analyzed in this research have cell sizes close to four times the minimum feature size square within the acceptable statistical margin of error.
Compared with DRAM technologies, in which cell sizes are either 6 or 8 times the minimum feature size square (6F2 or 8F2), NAND flash technologies have a smaller cell-size multiplier because of the simpler structure of the NAND flash cell. This is another reason why NAND flash technology has advanced ahead of DRAM.
Based on the NAND flash process trends observed by this analysis, NAND flash devices are generally one lithography generation ahead of DRAM devices. For example, the latest commercially available flash devices are in the range of 50 nm to 56 nm, but DRAM devices are available in the range of 66 nm to 68 nm (50-nm process node DRAM devices have been reported but have not been able to be confirmed at the time of this writing).
Key findings of this analysis are that:
• MLC technology, combined with advanced lithography, has been the driving force behind the widespread use of NAND flash devices.
• MLC technology at 50 nm has achieved 100-Mbit/mm2 bit density.
• The NAND flash industry made the transition from 70-nm, 8-Gbit to 50-nm, 16-Gbit technology in 2007.
• Both 16-Gbit and 32-Gbit NAND flash devices in 40-nm MLC technologies are expected within the year.
• NAND flash process nodes are generally one generation ahead of DRAM process nodes. NAND overtook DRAM as the process lithography leader approximately 18 months ago.
• Greater bit density is sought via 3- or 4-bit/cell technology or, in some cases, three-dimensional stacking.
• Upon the advent of 3- or 4-bit/cell technology, the role and importance of NAND flash controllers are expected to increase in order to compensate for complex read/write algorithms and higher ECC requirements.
• New applications, such as solid-state disks, have emerged as market segments for the NAND flash industry, bringing with them reduced production costs, diminished power consumption, improved reliability and stepped-up performance.
Young Choi (email@example.com) is memory technology manager at Semiconductor Insights, a CMP company specializing in in-depth technical investigation of ICs and electronic systems.