Intel’s Tri-Gate process uses its fifth generation of strained silicon engineering with raised source-drain and embedded graded SiGe for PMOS channels (which induces compressive strain) and embedded Si:C for NMOS channel (which generates tensile strain). Similarly, Tri-Gate represents Intel’s third generation of high-k/metal gates, which are now implemented in a FinFET structure.
Although the only major change from the 32- to 22-nm node is the introduction of Tri-Gate FinFET, this is not an incremental change. Rather, it represents a colossal leap. This advance is not only a major deviation in the 50-year history of planar transistors, but also a step into the realm of fully depleted channels.
Tri-Gate has several advantages. For example, the effective gate width is proportional to the fin height and can be increased without increasing the device footprint. Additionally, because the gate wraps around the fin, there is better control of the channel. The resulting device achieves high drive current, and low sub-threshold leakage current, verified in one of our electrical parameters reports. Another benefit is that the walls of the Tri-Gate offer a different crystallographic plane than the top of the fin. By orienting the Tri-Gate parallel or perpendicular to the "wafer flat," the mobility of the carriers can be influenced. Here, the PMOS transistors benefit from the higher mobility along the fin sidewalls.
The Tri-Gate structure brings with it process integration challenges. Epitaxial SiGe and Si:C islands have to be grown in a recess in a narrow Si fin rather than in an Si substrate. The fin pitch determines the transistor area and also brings constraints to the tilt angle of source and drain implants. One constraint is due to double patterning, which requires that all the fin pitches be the same size; if a larger gate width is required, then multiple fins have to be employed.
That means gate width is dependent on integral units of fins.
In their six-transistor SRAM cell, Intel decided to make the widths of pull-down (PD) transistors greater than the widths of access transistors (AC). Therefore, two fins are employed for the PD transistor, while a single fin is used for the AC transistor. The figure below shows a topographical image of the 6T SRAM, where N1/ N2 are NMOS_ PD; N3/N4 are NMOS_AC; and, P1/ P2 are PMOS pull-up (PU) transistors. Each N1 and N2 have two fins and the remainder have one fin only.
Figure: Topographical SEM image of the 6T SRAM array at the fin level with metal gates removed. The SRAM unit cell has been annotated; the SRAM array contains thousands of identical unit cell repeated in horizontal and vertical directions.
We can add as many cores as we like, but eventually we need a breakthrough in technology where size is no longer the issue. When are we going to follow Moore's law on processor frequency? I'm on Typofile: http://typophile.com/user/204946