Fin patterning is not straightforward; the fin is patterned directly on the Si-substrate and the STI structure and fin are etched simultaneously. Usually, STI structures have a positive taper for easier gap fill, while fins with vertical walls are preferred by theory and model simulations. For this reason, a multi-step etch process is suggested for these features. However, Intel’s fin cross-section (see figure below) resembles a solid trapezoid rather than a thin rectangle. The 18-nm-wide bottom provides a reliable base for the fin while its narrow top (just 7 nm wide) is appropriately rounded.
This feature geometry helps to avoid electrical field concentration in the corners. A small step at the onset of the STI structure may be an indicator of a thermal oxidation that was likely used to repair the etch-induced damage and define fin geometry (fin thinning and top rounding). The figure below shows that the high-k gate dielectric and work function metal layers wrap around the fin. There are several barrier and work function metal layers, and a thick W gate fill layer. All these layers need to be filled in a high aspect ratio trench.
Figure: TEM cross-section perpendicular to Si fin and along a metal gate. High magnification image of the fin reveals atomic planes of mono-crystalline silicon fin (lick on image to enlarge).
The aspect ratio can be estimated from the cross-section taken parallel to the fins (shown in the figure below). The gate length is about 30 nm and the depth of the trench during processing is about 110 nm, which leads to an aspect ratio of 3.5. After the deposition of work function metal, the aspect ratio increases for the deposition of W, as the width decreases but the height remains the same. In future generations, when the gate trench becomes narrower, the problem of metal gate fill may arise leading to gate conductivity problems. The Structural Analysis Report of Intel’s 22 nm Ivy Bridge processor from UBM TechInsights discusses in greater detail the work function materials, their composition; process flow and a complete review of the ten levels of metal interconnects.
Figure: TEM cross-section of PMOS and NMOS transistors in a direction parallel to their fins, highlighting the high aspect ratio for the replacement metal gate.