Once upon a time in the land of SRAMs, one asynchronous architecture fit nearly all applications. Today, however, the name of the game is "specialized." Indeed, "SRAMs are becoming almost niche-oriented," said Pat Lasserre, SRAM strategic marketing manager for Integrated Device Technology Inc. (IDT; SANTA CLARA, Calif.). That's as it should be, if designers are going to squeeze out the best performance they can from the products they build.
Thus, cellular phones have become the target for "slow," low-voltage, low-power asynchronous SRAMs that extend battery life, as well as for multichip packages that save space by combining SRAM and flash memory die.
Similarly, the latest high-speed data-communications designs are moving to fast and, most recently, bus-efficient synchronous SRAMs. In the process, such memories are displacing their fast asynchronous counterparts, which nevertheless continue to feed the lion's share of the SRAM market for existing or less demanding designs in communications, computing and test equipment. And for blindingly fast data access, a new breed of so-called late-write and double-data-rate (DDR) SRAM architectures is meeting the cache performance demands of workstations and high-end servers.
Amid this diversification, however, some overriding trends do appear, including increased bit capacity, wider word widths to match processor buses, shorter access times, dropping supply and signal voltages and shrinking package size.
Lured by the hopes of high-volume sales into the hot market for wireless communications gear like cell phones and other portable electronics, more than a few vendors are competing to sell slow but power-stingy asynchronous SRAMs with access times in the neighborhood of 35 ns. Among them is Mitsubishi Electronics America Inc. (SUNNYVALE, Calif.), whose low-power SRAM family spans 1 to 4 Mbits and features by-16 organizations, operating voltages down to 1.8 V (for the 1-Mbit M5M51R16), access times to 55 ns (for the 2-Mbit M5M5V216A) and chip-scale packaging (CSP).
For cell phones and other apps tight on space, Mitsubishi offers its 4-Mbit SRAM stacked in a molded CSP with 16 Mbits of flash. Similarly, Sharp Microelectronics of the Americas (Camas, Wash.) last year announced volume production of its stacked 2-Mbit SRAM and 16-Mbit flash CSP devices, and more recently added combined 4-Mbit SRAM and 32-Mbit flash parts to the list.
Forthcoming from Mosel Vitelic Corp. (SAN JOSE, Calif.) are combinations of its 2-Mbit SRAM with 4- and 8-Mbit flash chips. Similar multichip packages have been announced by Toshiba America Electronic Components Inc. (Irvine. Calif.), which says its technology will accommodate 2- to 16-Mbit SRAMs and 16- to 128-Mbit flash memory in by-8 and by-16 configurations.
Also pursuing the portables market, Cypress Semiconductor Corp. (SAN JOSE) last December rolled out its MoBL family of low-power SRAMs operating from 3.3 to 1.8 V with 70-ns access times at 2.7 V; 100 ns at 1.8 V. Typical standby current is only 1 microamp. Organizations of by-16 (CY623136V) and by-8 (CY623138V) are available in the first 2-Mbit chips, with 4-Mbit versions forthcoming.
Other SAN JOSE-based vendors offering low-power asynchronous SRAMs include Mosel Vitelic with its 256-kbit (32k x 8) V62C218256, a 2.3-V chip available with 35- and 70-ns speeds, and its 1-Mbit V62C1881024, a 1.8-V part available in 90- and 120-ns grades; Hyundai Electronics America, with devices ranging from 64 kbits to 4 Mbits, operating voltages from 5 V down to 1.8 V, and by-8 and by-16 outputs; Hitachi Semiconductor (America), offering similar bit densities and word widths as well as voltages to 3.3 V; and Samsung Semiconductor Inc., spanning 256-kbit to 4-Mbit densities.
Not surprisingly, many of these same companies also sell high-speed asynchronous SRAMs, with typical access times of 10 ns or less. Like their slower, low-power cousins, this breed is moving to higher densities, lower voltages and wider word widths.
In the workhorse 4-Mbit devices, supply and signal voltages are down to 3.3 V. And while some vendors, like IDT, see 4 Mbits as the end of the road for fast asynchronous SRAMs as faster synchronous devices gain ground, others, such as Samsung, are pushing ahead to 8 and 16 Mbits.
Among the more interesting fast asynchronous SRAMs to appear of late is a 3-Mbit, 9-ns chip organized as 128k x 24 bits. Introduced last month, the 3.3-V IS61LV12824 from Integrated Silicon Solutions Inc. (SANTA CLARA) offers a by-24 output, in effect consolidating the multiple memory chips needed to feed popular DSPs that have a 24-bit bus.
Though quite large, the total annual market for fast asynchronous SRAMs-one vendor pegs it at $700 million-is matched by the market for faster synchronous SRAMs. What's more, where the asynchronous sector is declining, synchronous parts are riding the wave of the high-speed datacom and telecom markets to an explosion in sales. Yet within the synchronous realm, one category-pipeline-burst architectures (PB-SRAMs), commonly used for L2 cache in personal computers-are seen to be fading as processor vendors put that L2 cache on-chip.
"Even though the market for L2 cache is huge, it is saturated and going to the end of its life. It is a sunset market," said Andre Hassan, general manager for memory products at Mosys Inc. (SUNNYVALE). The company manufactures 4- and 8-Mbit PB and flow-through SRAMs for PCs, including by-64 devices for notebooks, at frequencies that will exceed 200 MHz later this year. Mosys' claim to fame, said Hassan, is a one-transistor memory cell that speeds bit-density increases.
"If someone gives us an excuse to go to 32 or 64 Mbits, we could," he said. Still, it was Sony Electronics Inc. that introduced the industry's first 16-Mbit SRAM last November, the 111-MHz CXK77V80160TM-0 for supercomputer and networking applications.
At the same time, communications-equipment vendors, looking for a superior alternative to low-cost, widely available PB-SRAMs, have begun to design-in a relatively new type of bus-efficient SRAMs. So-called zero-bus-turnaround (ZBT), no-bus-latency (NoBL) and NtRAM Samsung's no-latency SRAM architectures cut through the pipeline delay that PB-SRAMs suffer when alternating between read and write operations.
Backing the ZBT approach are IDT, which coined the name; Micron Technology Inc. (Boise, Idaho); and Motorola Semiconductor Products Sector (AUSTIN, Texas). IDT's 100-MHz, 8-ns flow-through (IDT71V547) and 133-MHz, 4.2-ns pipelined (IDT71V546) 4-Mbit ZBTs are just over a year old, and the company expects to roll out 8-Mbit parts later this year. For its part, Micron has announced 8-Mbit samples in by-16, by-32 and by-36 organizations and 150-MHz clock rates. And Motorola offers ZBT versions of its extensive PB-SRAM line, with plans to introduce by-72 organizations.
Of the other bus-efficient types, NoBL SRAMs are produced by Cypress Semiconductor, and NtRAMs by both Samsung and Toshiba. Samsung touts the 2.5-V operating voltage of its 8-Mbit KM736S849T and promises a 16-Mbit version later this year. Both 100-pin thin quad flat packs and 119-pin ball-grid arrays are available.
To drive up the density and performance of its SRAMs, Toshiba is moving to a 0.25-micron full CMOS process, which is said to draw 0.2-micron lines. That process and its evolution, in turn, are powered by the company's flash and DRAM businesses, according to business-development manager Scott Nelson. By shrinking its DRAM technology to 0.175 micron later this year and 0.15 micron by the end of 2000, Nelson said, Toshiba expects to best serve both the high-performance and the low-power segments of the SRAM market.
Unbridled speed is the prime requirement for SRAMs that make up the L2 cache in workstations and servers. Here, so-called late-write and DDR architectures prevail, and the main players include Micron, Motorola and Sony. No doubt the most dramatic product announcement in this arena is Motorola's, which uses copper interconnects-an SRAM industry first, it says-in the ultrafast 8-Mbit, 333-MHz MCM63R836FC. The device is now in production, selling for $165 each in quantities of 10,000. By-18 and by-36 organizations are available.
A key advantage of using copper is reduced power dissipation-about 50 percent less than comparable Bi-CMOS SRAMs, said product marketer Geoff Waters. Riding the same copper technology is the company's upcoming 4-Mbit late-write version and, later, 8- and 16-Mbit DDR SRAMs that are said to clock at a stunning 666 MHz.
Sony's late-write and DDR SRAMs-8-Mbit DDR versions should be in production by this time-are an option for designers who need fast cache chips. But the emergence of ultrafast DDR, while a breakthrough for SRAM makers, slams the ball into the system designer's court, said senior manager Hiro Ino. "The challenge we overcame was in creating the silicon," he said. "Now the challenge falls to the system designers, who must get that kind of bandwidth at the board level." There, said Ino, signal-integrity issues, like noise, "still need to be resolved."
Cypress Semiconductor Corp.
EETInfo No. 605
Hitachi Semiconductor (America) Inc.
EETInfo No. 606
Hyundai Electronics America, SAN JOSE
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Integrated Device Technology Inc.
EETInfo No. 608
Integrated Silicon Solutions Inc.
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Micron Technology Inc.
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Mitsubishi Electronics America Inc.
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Mosel Vitelic Corp.
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Motorola Semiconductor Products Sector
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Samsung Semiconductor Inc.
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Sharp Microelectronics of the Americas
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Sony Electronics Inc.
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Toshiba America Electronic Components Inc.
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