ATLANTIC CITY, N.J. Genesys Testware has added multifrequency, built-in at-speed testing capability to its Logic BistCore product in an effort to reduce defect levels in 0.25-micron ICs. Logic BistCore is a library of parameterized, synthesizable, register-transfer-level designs used to implement built-in self-test hard cores and on-chip logic.
"Semiconductor manufacturers are reporting much lower yields for ICs fabricated in a 0.25-micron process, compared with those manufactured in 0.35 micron," said Bejoy G. Oomman, president of Genesys Testware. "Because the defect level increases exponentially with yield loss, it is essential to achieve nearly 100 percent defect coverage during manufacturing test."
According to Oomman, delay defects, which are a small fraction of the defect population, have been mostly ignored so far. "It is impossible for even the most expensive automatic test equipment to perform at-speed testing on ICs manufactured using 0.25-micron pro-cesses," he said.
Logic BistCore can detect delay faults in deep-submicron ICs, augmenting stuck-at fault tests created by an automatic test-pattern generation (ATPG) tool. Genesys says Logic BistCore products work seamlessly with logic synthesis tools from Synopsys, Cadence, Avanti and Mentor Graphics.
The products include parameterized self-checking testbenches, which can verify the operation of the BIST circuit using any VHDL (IEEE 1076-1993) or Verilog (IEEE 1364-1995) compliant simulator.
"Logic BIST complements scan ATPG in high-level design flows to achieve high defect coverage," said Taher Abbasi, vice president for products and technology at Bytek Designs Inc., a design services and training company.
Bus frequencies of many ICs fabricated in 0.25 micron can exceed 100 MHz and core frequencies, 400 MHz. System-on-chip designs also contain several reusable cores operating at different frequencies. For example, an IC could have a 500-MHz system clock, 125-MHz bus clock and 250-MHz core clock. A BIST circuit with a very flexible clock control scheme is essential for at-speed tests on such complex ICs.
Logic BistCore can create clocks whose period is an integer multiple of the master system clock, using a sophisticated glitch-free clock gating network. It can also synchronize different scan chains on different clock domains operating at different frequencies.
Designers of large ICs can continue to use their proven scan ATPG processes to achieve high stuck-at fault coverage, along with Logic BistCore to achieve high delay-fault coverage.
Another major stumbling block to the widespread adoption of logic BIST in large ICs, according to Oomman, is the problem of signature corruption due to unknown states (X) produced by the circuit under test. Logic BistCore incorporates elaborate response-masking capabilities to solve that problem without making any changes to the device being tested. Traditionally, gate-level test point insertion (TPI) has been used to improve the effectiveness of logic BIST. Modern logic synthesis tools now produce a gate-level netlist and a placement file concurrently, with accurate area, timing and power estimations. But gate-level TPI can invalidate synthesis results, causing problems in timing convergence. Logic BistCore incorporates proprietary test circuitry that can achieve high fault coverage without gate-level TPI.
Multifrequency at-speed testing is a core feature and is not separately priced. An end-user site license is $50,000 to $60,000, with mandatory 15 percent maintenance for up to 10 designs that reach silicon per year. Higher maintenance levels apply to sites with higher design volumes.
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