The International Test Conference opens this week in a new venue-Atlantic City-but attendees do not have to gamble on the technical program or the product rollouts vying for attention on the exhibit floor. They will be able to bank on the availability of content aimed at solving the many problems faced by those who are responsible for test.
Once again the exhibits will emphasize advanced production test equipment, with about 100 vendors displaying their automatic test equipment (ATE) and other wares. Some of those products will be featured in this week's Test section on pages 154, 156 and 157.
Vendors face a formidable number of problems, including diminishing access to internal chip nodes or pc-board points; clock speeds racing toward 1 GHz; buses extending beyond 100 MHz; and less time to develop test programs to test and wring out complex chips and boards on the production line.
ATE vendors are fighting back with both hardware and software. For example, Credence Systems Corp. will show its KalosXP (for eXtended Pins), a system that features 50-MHz performance and a wider 96-pin test site, thereby enabling the testing of high-pin-count NVM devices, with up to eight test sites operating in parallel.
Hewlett-Packard's HP 95000 High-Speed Memory test system, meanwhile, stretches to what's being called an "unparalleled" 32-site RDRAM production test capability. HP will also introduce a lower-cost member of its HP 93000 SOC test system, a mixed-signal platform that can test image-processor ICs, an RF IC/wireless IC test system and a system-characterization tool that validates high-speed digital designs at up to 1-Mbit/second data rates.
On another front, Schlumberger will unveil the IHS 1000th, which it calls "the world's most advanced thermal control test-handling system" (see story below). The claimed benefit is its high testing accuracy in the volume semiconductor production environment.
The program theme at ITC this year is "Test and the Product Life Cycle," a fitting title encompassing the ever more complex chips, boards and systems that are coming to market in ever more compressed product cycles.
Pat Gelsinger, a vice president at Intel, will kick off the conference by addressing the challenges that the World Wide Web poses for design and test. Following the key-note, 41 sessions will pick up the gauntlet and spell out some of the methodologies proposed and deployed by those engineers who are working to break through the test barrier.
Some of the more important topics include microprocessor testing, high-level test generation, embedded memory and core testing, system testing, microelectro-mechanical system fault modeling, mixed-signal built-in self-test, analog test, virtual test software, Iddq test, advanced system-on-chip test solutions, and design validation and analysis.
As in past years, the technical program is bolstered by a series of all-day tutorials on key topics-16 of them this year alone. Among the topics are the fundamentals of digital semiconductor testing, a comparative analysis of design-for-test (DFT) techniques, test strategies for high-density packages, and the new validation and test problems that arise with high-performance deep-submicron circuits.
Three lecture series that are a new element this year aim to underscore the conference theme. The lectures will address the time-to-market issues connected with DFT, the effects of chip-level DFT onboard test and the additional complexities of system test.
Finally, during the conference's 11 panel sessions, experts will debate some hot issues confronting design and test engineers. Those include interconnect testing, the value of Iddq for submicron circuits, and designing for reliability.
In addition to the new ATE offerings, a number of EDA and other vendors will roll out fresh products in design-for-test/ The lineup includes Asset Intertech, ATG Technology, Fluence Technology, Genesys Testware, HPL, JTAG Technologies, LogicVision, Mentor Graphics and Synopsys.