PALO ALTO, CALIF. Agilent Technologies Inc. will launch two high-speed bit error rate testers (Berts) for characterizing, verifying and testing optoelectronic and high-speed digital components at the Optical Fiber Conference in Baltimore the week of March 6. The 86130A BitAlyzer is a general-purpose serial 3.6-Gbit/second tester, while the 81250 ParBERT is a modular, parallel 2.6-Gbit/s model. Agilent says engineers can test 40-Gbit devices back to back, in parallel, using the 81250 ParBERT, which provides up to 64 parallel stimulus and 64 error-detection channels at speeds up to 2.66 Gbits/s. It also provides chip control signals, divided or multiplied clock signals, and operation at 1 Mbit/s to 2.6 Gbits/s with proprietary formats, as well as low-voltage differential-signaling (LVDS) load generation or analysis. For designers who need to test SAN-related multiplexers or demultiplexers, including Gigabit Ethernet, the combination of the 81250 ParBERT, 86130A BitAlyzer and 86100A Infiniium DCA helps solve physical high-speed design problems, Agilent said. The 81250 ParBERT is available now, starting at $70,000. The 86130A BitAlyzer will be available in April, starting at $110,000.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.