Chip-scale packaging (CSP) has been a hot technology for years now, but it's just beginning to make a broad impact in high-volume applications. Wireless portable products are fueling demand for chip scale, prompting a growing number of semiconductor makers to turn to a number of contract electronics manufacturers that provide this compact packaging alternative.
CSP provides just enough of a package to protect the die, but the total package usually isn't more than 20 percent larger than the device itself. While that's a common definition, it isn't always adhered to, since some parts have the tight spacing of CSP yet are a bit bigger. Regardless of how it's defined, CSP is gaining acceptance rapidly. Shipments are expected to grow from less than 2 billion units last year to 6 billion in 2002, according to TechSearch International (Austin, Texas).
That growth won't come without focused thought from design engineers. Those who work at the circuit-board level have many options from which to choose, and many issues to consider. CSP offers major space savings and it's easy to handle during manufacturing, yet there are serious considerations for those who want or need those benefits.
Nonetheless, contract manufacturers large and small currently are seeing solid growth in their CSP volumes, quite a change from just a year ago.
"Historically, Amkor started developing flip-chip chip-scale packaging in May 1999, and we qualified the technology in late 1999," said Richard Groover, vice president of flip-chip development at contract manufacturer Amkor Technology Inc. (Chandler, Ariz.). "We now have a 7-millimeter package size that's in the same footprint as our chip array BGA 9ball-grid array. There are 49 I/O on the substrate side and 152 bumps on the die side. It's for a PC-type application, a voltage regulator. That part is running at about 60,000 pieces per week."
As that one chip-scale part runs in high weekly volumes, Amkor is looking at a number of other contracts. Within the next several months, Groover said, he expects to see quite a few more programs start moving into production. "We have 17 active customers, most of them somewhere in the qualification mode, although some are still in the design phase," Groover said. "The body sizes for those parts goes all the way up to 12 x 12 mm, with die sizes up to about 10 x 10 mm in chip-scale packages. Some of those programs are in the PC world, but most of them are in handhelds, cell phones and PDAs."
That focus on portable products is also being seen at other contract manufacturers in packaging. "In the first quarter of next year, we will be on a 10,000 wafer per quarter rate," said Jim Young, executive vice president of business development at Intarsia Corp. (Fremont, Calif.). "Right now, we're probably doing 1,500 to 1,800 wafers per month, so we're expecting to double production pretty soon. People are doing everything from integrated passives to memory stuff. Mainly what drives this is wireless because they need the size benefits of CSP. When we try to sell into notebooks they are not nearly as interested as people doing wireless portables."
Intarsia has a bit of a different business model than many other suppliers. Its main focus is on integrated package devices, which not coincidentally are packaged using CSP. However, the company has some excess capacity that it's selling.
"We're a manufacturer of products targeted at wireless products, but we have chip-scale capabilities. It's not our main business, but if you have extra capacity, you sell it," Young said. "If the business makes sense, we'll do it, but we're not hanging out a shingle that says we're a foundry. We'll limit that business to probably three customers this year, and we've got two now."
Most observers expected the market to take off sooner, given all the publicity about this compact packaging technique. Now that it is taking off, there might be some problems getting chips put into CSP form, but most vendors don't expect it to become a serious problem. "Right now, we're starting to see things take off. It's a year after we expected it, but now it's a scramble to keep up," Young said. "Industrywide, there might be some short-term shortages, but I don't expect to see any in the long term. With the wireless industry, there are no gentle slopes. It just takes off."
Both the chipmakers and their end customers fuel that demand. One device provider has found that customers want chips that have relatively low lead counts. "In the last six months, we've started using chip scale, we've seen demand that is pretty large," said Tim Colleran, director of corporate marketing at Altera Corp. (San Jose, Calif.). "We're selling parts in a U49 package, with ultrafine lines and a 0.8-mm pitch on the solder balls. It has a 7 x 7 grid of balls. We also have an ultrafine line U169 package that we have a few products in."
Like any new technology, CSP has roadblocks. One is the proliferation of CSP techniques. In addition to the many alternatives provided by contract manufacturers, there are several others developed by semiconductor makers who package their own devices. Some observers reckon there are around 50 different styles. This makes it particularly difficult for those who are trying to develop industry standards.
"The infrastructure is not totally in place," said Dieter Bergman, technical director at the IPC (Northbrook, Ill.). "Everything keeps changing because there are new players in the arena." While that's a negative for some, others don't think it's so bad. "There are still 50-plus variations of CSP out there," Groover said. "That's good for a contract manufacturer, we can offer something for everyone. Almost. We can't offer 50 varieties but we can offer plenty."
Along with the lack of standards, another obstacle is one that is identical to CSP's key benefit-the package is small and the solder balls are very close together. That means that designers who want the smaller size are going to have to spend a bit more time designing their board layouts. Most engineers won't do that for just one CSP device.
"You're hard-pressed to get a customer to adopt chip scale for just your product," Colleran said. "People who have a real need adopt it on a broad basis. Typically, we see CSP making board design more difficult. The ball pitch is much tighter on the circuit board, so it's more complex to place and route."
That creates a trade-off for engineers. In a nutshell, they have to decide whether to go with small size or higher costs.
"Designers tend to need more layers when they use chip scale," Colleran said. "When you look at the U49 package, with a 7 x7 grid of balls, you need to get 49 traces in a small area. With a 48-pin QFP, you're looking at two layers. With the U49, you're definitely in three, and possibly four layers. If you go to bigger packages, say 12 x12 or 15 x 15, it's that much more of a problem to get traces to the center of the package."
As a chipmaker selling parts to board-level companies, Colleran is far more in tune with the obstacles than are those who focus on packaging alone. He noted that while some board manufacturers can integrate CSPs, others can't.
"CSP parts are harder to handle," Colleran said. "There's a certain class of contract manufacturers that can support chip scale, and a certain class of contract manufacturers that can't."
Among the other positive attributes that CSP brings to the party is that the signal paths between components are far shorter than with fine-pitch leaded parts. The paths inside the package itself are about as short as possible, and the small package sizes mean that devices can be positioned closer together. That is beneficial for very fast devices. "Most recently, there's been a lot of activity in high-frequency parts, from 10 way to 77 GHz," Groover said. "We're extending flip chip into packages that are electrically good up to 10 GHz. That's flip chip inside the package and chip-scale mounting on the outside."
While manufacturers push technology forward, they've also got to think about at least a couple of other features that are near and dear to design engineers. Without low cost and high reliability, a technology won't get far.
Unitive Advanced Semiconductor Packaging (Research Triangle Park, N.C.) has addressed costs by devising a copper redistribution process that provides as much as 30 percent savings over alternative backend metallization processes. By using copper with a polymer designed to permit using copper for interlevel dielectrics, Unitive can meet the needs of those with high-frequency requirements or those integrating passives. The process can permit line and spacing dimensions of 12 and 13 microns, respectively.
Unitive has also reduced soft errors caused by alpha particles. That's particularly important in chips with gate dimensions of 0.18 micron or less. Techniques for eutectic and high-lead solder provide greater than an order of magnitude improvement in reducing soft errors.
Still, the key attraction of CSP is its fine-pitch capability. When BGAs took off a few years ago, engineers were excited about ball pitches that were 1 mm or finer. With the move to chip scale, that seems closer to the device size than to the contact spacing.
"Right now, 0.5 mm is the smallest pitch that most people are considering," Groover said. "There's a little talk about going below 0.5 mm, but that begins to impact your ability to mount parts."
When high frequencies and fine spacings are combined, it may open the door for a new substrate. Although it's not exactly a new material that designers are implementing instead of the organic laminate substrates that now dominate the chip-scale world.
"People are looking at ceramics instead of laminates, largely because it's easier to do your routing on ceramics," Groover said. "Ceramic suppliers have introduced high thermal coefficient of expansion (TCE) ceramics that match up better with circuit boards. Solder reliability is much better with that. That surprised us, initially we hadn't done anything in ceramic, but we're getting a lot of interest from the RF people."
This interest keeps prompting more companies to get involved in CSP. Given the huge number of alternatives out there, most companies have decided not to develop their own. Instead, many chip suppliers and contract manufacturers license CSP techniques.
One early proponent of CSP, Tessera Inc. (San Jose, Calif.), has pushed its compliant substrate technology forward via licenses to Advancec Micro Devices, Intel, ST Microelectronics, Hitachi and Toshiba.
Flip Chip Technologies, a Phoenix joint venture created by Delphi Delco Electronics Systems and Kulicke & Soffa Industries, recently licensed its Ultra CSP technology to California Micro Devices Corp. (Milpitas, Calif.) and to Siliconware Precision Industries Co. Ltd. (Taichung, Taiwan). California Micro will use the technology for integrating passives, putting scores of discrete passives and electrostatic devices in 28-pin packages to provide huge space savings in passive-heavy products like communication products.
But even companies that succeed with licensing have to keep pushing technology. The latest advance from Tessera is a series of test vehicles that use lead-free solder techniques. Environmental concerns have prompted manufacturers to begin serious research in the lead-free world. Lead-free processes are currently being examined by groups throughout the packaging and manufacturing world, including the IPC, the Interconnection Technology Research Institute (Austin, Texas) and the National Electronics Manufacturing Initiative (Herndon, Va.).
Since this research has not driven suppliers to a single de facto standard, Tessera has developed test vehicles designed for two lead-free solders. Tessera is preparing modules with a third alloy.
While improving technology is a key to the future of Tessera and its licensees, the company is also involved in some actions designed to make sure that it retains control over the technologies, both technically and financially. Tessera is suing Texas Instruments and Sharp for patent infringement.
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