San Jose, Calif. - A 9-Mbit, dual-port RAM from Cypress Semiconductor can buffer large packets of data in two independent clock domains and provide simultaneous read and write access to any of its memory cells from either of its two ports.
The 256k x 36-bit-wide CY7C08D53 "Dense" RAM operates at up to 83 MHz, provides up to 6 Mbits/second of synchronous, pipelined memory bandwidth and can easily be interfaced to wide buses, said Chris Norris, vice president of Cypress' Data Communications Division. The RAM is aimed at wide-area networks, storage networks and wireless basestations.
Norris said high-density, multiported memories are used in many communications applications for data packet buffering between the backplane interconnect and the data port.
"The multiport memory is used to store and manipulate packet data between baseband processing and digital signal processing system devices operating at different clock speeds," he said. "When there's a difference between the input and output data speeds, a buffer helps pre-|vent loss of data and helps maintain efficient flow control. The greater the difference between the input and output clocking speed, the greater the need for buffering capacity."
Norris added that the memory's top operating speed of 83 MHz enables it to stay ahead of the PCI bus "sweet spot" of 67 MHz. The device can also be used with a complex programmable logic device that controls the memory's data flow and partitioning.
Alpha samples of the part are available now. Production is planned for the second quarter. The device is packaged in a 24 x 24-mm, 176-pin TQFP and is priced at $97 in quantities of 10,000.
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