Santa Clara, Calif. - Integrated Device Technology Inc. last week unveiled its densest and fastest dual-port memory to date-a 9-Mbit, "bank-switchable" synchronous device that operates at up to 166 MHz at 3.3 volts and supports data transfer rates of up to 12 Gbits/second. IDT also introduced 2-Mbit and 4-Mbit bank-switchable devices.
Strategic marketing manager Bill Beane said the new memory components are designed for applications in which two devices-microprocessors, digital signal processors, ASICs or field-programmable gate arrays, for example-can effectively share the same memory. A dual-port memory costs less, occupies less space and consumes less power than would dedicated memory configurations for each device.
Beane noted that two devices could share a common SRAM through a single port, but would have to take turns accessing the memory. IDT's dual-port architecture allows simultaneous write access from each device, albeit to different addresses, as well as simultaneous read access. Each port has its own control, address, clock and I/O pins. Designers can allocate as much of the memory as they wish to either device.
The 2-Mbit parts are available in 64k x 36 or 128k x 18 configurations, with parity bits available for error detection and correction. Each configuration is priced at $59.94 for 133-MHz performance, in quantities of 10,000.
The 4-Mbit parts are available in 128k x 36 and 256k x 18 configurations, priced at $84.36, and the 9-Mbit parts are offered in 256k x 36 and 512k x 18 configurations, priced at $118.74.
Packaging options include a 15 x 15-mm, 208-pin BGA with an 8-mm ball pitch; a 17 x 17-mm, 256-pin BGA with a 1-mm pitch; and a 28 x 28-mm plastic quad flat pack for customers that prefer a leaded package.
Beane said other dual-port memory components-including 2- and 4-Mbit IDT devices that are now being replaced-have extra row and bit lines in each cell. The bank-switchable architecture uses standard SRAM cell configurations, which lowers space, cost and power requirements.
"The memory chip is internally subdivided into 64 banks and, thanks to multiplexing circuitry, each bank can be accessed by either port as long as the bank isn't already in use," Beane said. Bank address pins control accesses to specific banks by asserting standard addresses. Designers can use software controls to define a smaller number of larger banks if desired. Byte controls allow designers to interface between systems of x36, x18 or x9 bus widths.
The memory features selectable 3.3- or 2.5-V I/O operations on each port, so it can work with new network processors and DSPs as well as with legacy devices. Beane said the simultaneous-access capability increases effective bandwidth while the synchronous interface simplifies designs, thus shortening time-to-market.
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EETInfo No. 623