Shelton, Conn. - A RISC-based system-on-a-chip (SoC) with embedded DD-AMPS firmware and a host application programming interface is available from TranSwitch Corp. for next-generation channelized DS3, DS1, E1 and DS0 access applications. The TEPro targets wireless access, multiservice access platforms, computer telephony, time-division multiplexing (TDM) over packet and echo-cancellation applications.
Product-marketing manager Brian Stroehlein said the SoC can support one DS3, 28 DS1 or 21 E1 line interfaces and can be configured for a variety of operating modes. Built around a RISC CPU, it integrates an M13/G.747 multiplexer including a DS3 framer with full C-bit functionality to support clear-channel DS3; a 28-channel DS1 framer; a 21-channel E1 framer; a 28-channel DS1/E1 cross-connect; a 672 x 4,096-channel nonblocking DS0 cross-connect for grooming, concentration, switching and multiplexing. Also on board are a message mailbox FIFO; a multichannel HDLC for Layer 1; and two SS7 and ISDN-PRI signaling and MVIP and H.100/H.110 TDM bus interfaces.
TEPro is priced at $148 in quantities of 1,000. Samples are due in the third quarter. The SoC is packaged in a 27 x 27-mm, 456-lead plastic ball grid array package.
Call (203) 929-8810