Chelmsford, Mass. - Mercury Computer Systems Inc.'s new RACE++ Series VantageRT FCN board offers signal- and image-processing capabilities in a package that includes field-programmable gate arrays (FPGAs) and PowerPC microprocessors connected by a switch fabric.
By configuring the VantageRT multicomputer with both FPGAs and PowerPCs, Mercury Computer engineers say they've endowed it with greater processing speed, primarily because certain types of computational operations run far faster on FPGAs than on PowerPC microprocessors. "FPGAs provide a way to beat Moore's Law," said Richard Jaenicke, director of product marketing for Mercury.
Among the applications that are well-suited for the FPGA-PowerPC combination are medical-imaging and radar signal-processing systems. Applied to CT-scanning equipment, for example, the system can be used for so-called "back-projection processing," where it enables the equipment to construct CT images in as little as one minute. "Algorithms for back projection can run about 40 times faster in an FPGA than in a PowerPC G4," Jaenicke said. "That speedup means that hospitals can start using their CT scanners in the emergency room, rather than in applications where it takes a day to get the results."
Initially, Jaenicke said that the VantageRT will also be employed in front-end radar and in signal-intelligence appli-cations. The part delivers scalable computing through a PCI-64 form factor combined with Xilinx Virtex II FPGA and dual PowerPC microprocessors in a VantageRT PCI module. The FPGA compute node contains a 3 million- or 6 million-gate Virtex II FPGA, up to 12 Mbytes of double-data-rate SRAM, 256 Mbytes of DDR SDRAM and 52 pairs of low-voltage differential-signaling (LVDS) I/O lines.
Each PowerPC compute node consists of a 500-MHz PowerPC 7410 microprocessor with AltiVec technology, 2 Mbytes of L2 cache, 256 Mbytes of SDRAM and a compute-node ASIC. The compute-node configuration allows system architects to partition applications for the best performance on FPGAs and PowerPC microprocessors running on the same board.
The company said that the FPGAs in the RACE++ environment become part of a scalable system that can expand to provide as many FPGAs and PowerPC microprocessors as applications demand, with minimal recoding and redeployment expense.
On each VantageRT FCN, the FPGA compute node has two 267-Mbyte/second connections to the module's RACE++ crossbar. Using the crossbar, the FPGA can communicate directly with either module's PowerPC processors or, using over-the-top RACE++ connections, communicate with other Vantage-RT modules.
"Once you have the data, you don't want the FPGA to be an island," Jaenicke said. "You need to be able to send it quickly, and be able to easily change which processor you're sending it to."
The system's configuration flexibility is enhanced by the front-panel streaming LVDS I/O interface.
Designed for application-defined communications, it can be used for direct FPGA-to-FPGA connections or to support other types of parallel I/O. With a cable length of up to 1 meter, it can support 600 Mbytes/s of data transfer, running at 200 MHz.
Pricing in OEM quantities starts at $15,800.
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