Lattice Semiconductor Corporation and Tyco Electronics announced the demonstration and interoperability of Lattice's XPIOTM 110GXS physical layer electronic transceiver with Tyco Electronics' FR-4 backplane and High-Speed long cables. The demonstration utilized Lattice's XPIO 110GXS 16-bit, 9.953 to 10.709 Gbps transceivers and Tyco's HM-Zd based QuadRouteTM backplane and ZFP-I/O high speed cables in conjunction with passive equalizer and active equalizer device.
"Using Tyco Electronics' interconnect solutions with our XPIO 110GXS to actually demonstrate signals driving over 16 inches (~406mm) and 30 inches (~762mm) of FR-4 backplane and/or at least 7 meters of ZFP-I/O cable assembly at speeds up to 10 Gbps NRZ is the best way to prove to customers the quality and reliability of our high-speed physical layer solutions," said Stan Kopec, Vice President of Marketing for Lattice. "This demonstration is a key step in bringing cost-effective 10 Gbps cable interconnect and electrical backplane solutions to market," added Kopec.
Tyco Electronics Circuit & Design engineers have optimized the channel losses of a backplane based on high-speed Z-PACKTM HM-Zd connectors with Lattice's XPIO 110GXS as an active interconnect using combined passive and active equalization technique. In addition, a high-speed cable assembly based on the ZFP-I/O connector was optimized to achieve reliable transmission over a distance of 7 meters using similar combined passive and active equalization technique.
The demo configuration at the largest electronics and IT show in Asia Pacific (CEATEC) was as follows:
A 9.953 Gbps serial NRZ-PRBS 211-1 bit stream was injected into the Lattice XPIO SERDES using a Pulse Pattern Generator. The XPIO then hooked to one end of a 7 meter long "ZFP-I/O" cable assembly through interface boards. A second XPIO SERDES was hooked to the other end of the cable through combined passive and active equalization. The XPIO outputs were individually connected to the DSO and BERT as single ended signals.
"We demonstrated a reliable and error free (BER better than 10-14 ) system interconnect at 9.953 Gbps that ran during the entire 5 days of the show," said Doron Lapidot, Director Circuit & Design Tyco Electronics - Asia/Pacific & EMEA.
"This is a breakthrough in 10G serial link NRZ-coded system interconnect since the solution also demonstrated full interoperability," added Lapidot.
"In today's competitive market, this cost effective and reliable solution is an excellent example of how our customers can utilize a flexible solution for system interconnect based on a combined solution," stated Minoru Okamoto, Vice President, Communications, Computer & Consumer Electronics of Tyco.
Lattice Semiconductor has developed the industry's broadest and fastest programmable device family for high-speed serial backplane data transmission. The ORT82G5 integrates eight backplane transceiver channels, each operating over a range from 600 Mbps to 3.7 Gbps with a full duplex synchronous interface with built-in Clock and Data Recovery (CDR).
Also included are embedded XAUI and Fibre-Channel state machines, bypassable 8B/10B encoding/decoding support plus multi-channel alignment capability without using any FPGA gates. The device features more than 400K FPGA gates and up to 372 general-purpose programmable I/O pins. The new ORT42G5 contains four backplane transceiver channels providing similar performance and FPGA density.
The ORSO82G5 includes eight backplane transceiver channels, each operating at up to 2.7 Gbps data rate providing a full-duplex synchronous interface with built-in Clock/Data Recovery (CDR) and more than 400K FPGA gates. The ORSO82G5 contains an embedded core for SONET data scrambling and descrambling, streamlined SONET framing, transport overhead handling, cell insertion and extraction, idle cell insertion/deletion plus the programmable logic to terminate the network into proprietary systems. All SONET functionality is hidden from the user and no prior networking knowledge is required.