SAN JOSE, Calif. " Ratcheting up the capabilities of its binary serializer/deserializer technology, Accelerant Networks announced Monday (Dec. 1) a 6.25 Gbit/second serdes with enhanced adaptive equalization. The part rounds out a family of binary, PAM4 and dual-mode serdes from the startup.
The AN6620 is a quad binary transceiver capable of handling 6.25, 5, 3.124 or 1.25 Gbit/s data rates using an internal, dual cross-connect that also enables multicasting support for simultaneous redundant switching. Accelerant said the part consumes less than 1W.
The use of binary technology opens the door to design wins in serial ATA, serial attached SCSI and PCI Express applications in addition to backplanes that have been the company's primary target market to date. Accelerant has multiple unannounced design wins for both its dual mode and binary serdes, said Bill Hoppin, vice president of marketing for Accelerant.
The company plans to roll out versions of its AN6000 series in 13mm2 packages in the second quarter and octal version in the third quarter, said Hoppin. About half today's backplane designs use standalone serdes, but that will move to about a third over time as more serdes get integrated into ASICs and standalone parts build in more intelligence, he added.
The AN6620 is built in TSMC's 130nm process and packaged in a 17mm2 quad BGA. Parts will sample early next year priced at $80 in volume.
The startup is now in the process of raising a new venture capital round that is expected to take it to profitability sometime next year.