Grappling with testability? Then check out what intellectual property vendor Intellitech Corp. (Durham, New Hampshire) is dishing up. The company now offers a unique IEEE-1149.1-compliant test and maintenance bus product it calls a PTC Addressable 1149.1 Gateway.
Intellitech's PTC (Parallel Test and Configuration) chip is designed for use in so-called blade circuit boards that plug into multi-slot or multi-cabled backplanes. The IC provides the infrastructure necessary for multi-board FPGA configuration, as well as board-to-board interconnect test.
"A key element..."
The PTC addressable 1149.1 gateway is billed by Intellitech CEO "CJ" Clark as a "key element in designing multi-board systems that can perform in-the-field upgrades to all non-volatile devices of the system. Clark should know; he's the IEEE-1149.1 group's past chairman.
"It's also a necessary element for performing tests of PCB to PCB gigabit SERDES and LVDS connections, and diagnosing connection problems to the pin.
"It can be used on blades targeted for proprietary telecomm backplanes or on boards used in standard backplanes such as cPCI, VME, or VXI," adds Clark.
Clark maintains that the Intellitech PTC is also the industry's only gateway device for 1149.1 test and configuration of multi-board systems that can scale with the size of the system. The diagram shows a typical serial bus at the board level.
The PTC's patent-pending parallel test capabilities using IEEE 1149.1 enable simultaneous test and on-board programming of all similar boards in a system. "This enables manufacturing circuit board tests to be re-used at the system level, during integration and burn-in without incurring test time penalties," says Clark.
Time Is Money
"Previous addressable multi-drop 1149.1 architectures lacked scalability," notes Clark. "If the test time for one board in a system was 45 seconds, for example, then ten similar boards would result in 450 seconds of test time. Each printed circuit board had to be tested one at a time."
Click for full-size schematic
"With Intellitech's patent-pending technology, the time to test those ten PCBs would only be 45 seconds", notes Mike Ricchetti, Intellitech's Chief Technology Officer. "It's particularly useful in that FPGAs and other programmable devices can be configured and verified simultaneously. It's not necessary to individually interrogate each device on each board to see if they were programmed successfully."
IEEE-1532, the in-system configuration standard, has become the preferred method of programming devices such as CPLDs (complex PLDs) and FPGAs. In these applications, Intellitech's PTC can shorten the design time for creating a multi-board IEEE-1532-compliant bus throughout a system.
Ricchetti notes that with a parallel FPGA configuration, a PTC can achieve higher FPGA configuration data rates than proprietary methods---with less design time and lower parts cost.
As an example, Ricchetti cites a case where FPGAs are configured at power-up using the FPGA vendor's proprietary 8-bit-wide interface. The proprietary interface supports programming the FPGA at data rates from 1-Mbit/s to 152-Mbits/s, with 80 Mbits/s typical.
However, this proprietary interface must be local to each FPGA, requiring configuration resources on each board in a system, increasing the parts cost. Using a 20-MHz test clock and the company's PTC architecture, Ricchetti says four PCBs can be configured from a single programming resource simultaneously, providing an aggregate data bandwidth of 80 Mbits/s, matching typical proprietary configuration data rates.
With just eight like PCBs in a system, the FPGA configuration speed over the serial PTC bus is 160 Mbits/s, exceeding the highest 8-bit-wide configuration data bandwidth.
Functional Testing Getting Expensive
As system complexity continues to increase, functional testing as the sole means of verifying product quality is becoming more complex and more expensive, too. Testing and diagnosing faults on high-speed differential signal, gigabit SERDES connections for jitter, noise, and crosstalk is a challenging task to accomplish with CPU-based diagnostic software.
Moreover, diagnosing backplane problems to the pin isn't possible without IEEE_1149.1-assisted structural test. As such, prudent OEMs are designing DFT (design for testability) into multi-board systems to enable PCB-to-PCB interconnect testing and 1149.1 assisted BIST (built-in self test) functions.
"We see IEEE-1149.1 as the test and maintenance bus used throughout the system to enable comprehensive system test and in-the-field updates," says Clark. "IEEE-1149.5 has been withdrawn as a standard, as it didn't address these issues or allow for scalable multi-vendor PCB test and configuration.
"In the past, serial EEPROMS and flash memory were updated in the field over several separate functional buses. This added to the complexity of the system and the engineering involved. Today, OEMs are seeking to lower overall product cost with a unified approach to in-the-field updates and multi-board test."
In line with that, Clack maintains that his firm's PTC device is the first IC of its kind to address this problem. The PTC was first designed into one of Intellitech's customer's system in 2000. "This early adopter now has systems deployed with up to 25 boards," says Clark, "each using a PTC and connected over our patent-pending parallel test bus."
Key PTC Features
Here's a summary of the key features of the PTC chip:
* Creates a flexible, scalable bus over standard 1149.1 for programming FPGAs
* Provides design independent infrastructure for updating non-volatile memory in a multi-board system, from a centralized point
* Enables simultaneous parallel test of similar PCBs in-system
* Enables system level JTAG test and FPGA configuration data rates of over 40 Mbits/s
* Enables reusable PCB-to-PCB interconnect tests over a backplane
* Supports board identification of multi-vendor PCBs in the system
* Support for four to eight local JTAG paths/PTC with programmable voltage levels
Pricing and Availability
The Intellitech PTC chip is available now from stock, packaged in VQ100, TQ144, and 256-pin BGA packages. Pricing starts at about $11 each/10K quantity.
A reference design is also available. It gives you four cPCI boards, a cPCI backplane, and a power supply, and is complete with schematics and FPGA design files. Its cost is $4,500.
For a summary paper in Adobe Acrobat (.PDF) format, click image
Contact CJ Clark at Intellitech Corp., 70 Main St., Durham, New Hampshire 03824. Phone: (603) 868-7116. Fax: (603)868-7119. More information can be found on Intellitech's Web site.