A DSP Synthesis tool has been introduced by AccelChip Inc. to accelerate the ASIC and FPGA development process by providing automatic implementation and verification flow for DSP algorithms.
The AccelChip DSP Synthesis tool gives DSP algorithm developers using a MATLAB-based flow a direct flow to silicon by generating synthesizable register-transfer language (RTL) code from MATLAB, according to the company. With AccelChip, DSP designers can use the MATLAB design as the golden source for driving synthesis and verification.
The AccelChip DSP Synthesis tool provides architectural exploration capabilities, including support for FPGAs, ASICs, and structured ASICs; enhanced flows with The MathWorks' Simulink, Xilinx Integrated Software Environment, and Xilinx System Generator tools; and support for AccelChip's parameterized DSP libraries. The enhancements create a flow between algorithm development and silicon implementation and extend the company's DSP synthesis to more complex designs.
According to a spokesperson, at the architectural level, the AccelChip DSP Synthesis tool allows designers to trade off area, performance. With its links to Simulink and System Generator, algorithms can be integrated into the complete chip. AccelChip DSP Synthesis allows designers to explore possibilities without touching their golden source. The tool's floating- to fixed-point conversion is designed to increase designer control over trade-offs between performance, area, and accuracy.
The AccelChip DSP Synthesis tool, which generates cycle-accurate models for a DSP-based component integration environment such as Simulink, enables system-level verification of components using libraries and math-based models. AccelChip DSP Synthesis exports simulation models that are verified against the golden MATLAB source into Simulink, enabling rapid system verification. AccelChip DSP Synthesis also works with System Generator, a system-level modeling tool that facilitates FPGA hardware design. This integration enables verification of AccelChip-generated modules with Xilinx's IP.
An option to AccelChip DSP Synthesis is AccelWare, a set of synthesizable, verified, fixed-point, digital signal processing (DSP) building blocks that supports a top-down MATLAB-to-silicon synthesis and verification flow for FPGA, ASIC, and structured ASIC design. AccelWare produces DSP components--such as FIR filters, FFTs, and encoders/decoders--directly from MATLAB.
AccelChip DSP Synthesis and AccelWare are available immediately. All existing AccelFPGA customers with an active support contract will receive an upgrade to AccelChip DSP Synthesis at no additional fee. For pricing, visit www.accelchip.com.