By Ron Wilson, EE Times
High-speed serial I/O connections are proliferating in system-level ICs, PC support chips and FPGAs, as the advantages of fast serial links gradually drive parallel buses off the board.
But in a typical display of industry forethought, not a lot of concern has gone into the question of how to test a 3-GHz to 6-GHz I/O structure without spending more than the market value of the chip doing it.
There have been basically two approaches so far, notes Tom Newsom, VP and general manager of Agilent Technologies Inc.'s Systems-on-Chip Business Unit.
The Conventional Approach
One has been the traditional approach: If you have a 5-GHz pin that needs testing, go get a 5-GHz RF tester. This is a wonderful approach technically, says Newsom, whose company sells a $20 million ATE system to do the job. But it's somewhat impractical in terms of cost-effectiveness, and leaves a test development group with a substantial development problem.
At the other extreme, many SoC (system-on-a-chip) designers have tried to duck the whole issue by building a loopback capability into their serializer/deserializer (SERDES) blocks. After all, most standards for high-speed serial I/O, including PCI Express and Serial ATA, specify quite clearly that pass/fail test capabilities must be built into the interface specifically for loopback built-in self-test (BIST).
Lots Of Escapes
But loopback BIST by itself also has problems, Newsom argues. It will provide a pass/fail indication for that particular match-up of transmitter and receiver, operating on a near-ideal loopback connection at a particular voltage and temperature point. If it's used for production test, there will almost certainly be large numbers of escapes of devices so close to the edge that they can only work with one another on the same die under identical conditions.
Newsom says test engineers have tried to work around this problem by running the loopback through the tester's load board, where they could do a limited amount of signal conditioning, or where the signals could be looped through a so-called golden reference device. This helps, but it's far from a general---or inexpensive---solution.
Agilent is taking a big step forward in this approach with its BIST Assist channel cards, which plug into the test head of its 93000 test systems. The card carries programmable mixed-signal circuitry that receives a signal from the device-under-test's (DUT) transmitter pin, conditions it under command from the test program, and returns it to the DUT's receiver pin.
About A Dozen Functions
About a dozen functions can be performed on the signal as it loops through, Newsom says. The big ones are dc-level manipulation, common-mode noise injection, AC-level modulation, and jitter injection. This gives the BIST Assist card flexible control over the signal as it loops from transmitter to receiver. The DUT's receiver still performs pass/fail tests on the signal---but this time the signal is manipulated by the Agilent card.
That's made possible by the high-frequency capabilities designed into the 93000 probe head, Newsom notes. The system, which can make direct digital tests at upward of 3 GHz, was designed from the beginning to move such signals around between pogo pins and the channel cards.
Newsom claimed that the BIST Assist approach would permit a 93000 series tester to be delivered into a 320-pin SoC testing application with the ability to do assisted self-test on 6.4-Gbit/s I/Os for under $1 million---a bargain, considering that a few years ago the semiconductor industry road map warned such a tester would cost $20 million by now.
The First Of The Breed
The BIST Assist card is the first in a number of test modules that are scheduled for the 93000 platform this year, Newsom says. The plan is to attack the most cost-intensive problems in SoC test with an architected teamwork between on-chip intellectual property and new tester capabilities.
This strategy has enormous potential to save both tester initial cost and time on the test head, Newsom said. But he warned that it depended on early and detailed involvement of test architects in the chip design process. "If it ain't architected in, it ain't gonna work out."
And this, in turn, is gradually drawing Agilent into new ways of engaging with design teams, Newsom said. From consulting on tester capabilities, the company is gradually finding itself brought in to consult on test strategies.
As BIST Assist illustrates, the full solution to the SoC test problem can't be arbitrarily partitioned at the edge of a die. Even built-in test may require external active subsystems, just as ATE may no longer be practical without cooperating circuitry on-chip.