Dallas -- Motorola Inc.'s Freescale Semiconductor entity announced updates of its PowerQuicc II Pro and PowerQuicc III families at the Smart Network Developers Forum Tuesday (April 27).
The two architectures, based on the e300 and e500 PowerPC cores, respectively, each added encryption blocks, and Motorola said it plans announcements soon on e700 cores as well.
The latest PowerQuicc II Pro device, the MPC8349E, is the first family member to support a 64-bit double data-rate SDRAM controller and the first to offer dual Gigabit Ethernet controllers on-chip. The processor, based on a G2 PowerPC core and built in a 130-nanometer process, offers 32 kbytes each of data and instruction cache and operates at up to 667 MHz.
The equivalent processor in the PowerQuicc III family is the MPC8541E, which combines an e500 core with 256 kbytes of L2 cache, a 64-bit DDR controller and dual Gigabit Ethernet controllers. The 8541 offers dual 32-bit PCI controllers, which can independently control different peripherals or be configured to form a 64-bit interface.
The two PCI controllers can be operated at different frequencies, sparing the expense of using a PCI bridge in a design, the company said.
"There will be some overlap in the target designs for the e300 and e500 cores, but there will always be a performance and price difference that will drive the PowerQuicc III into higher-end switches and routers," said director of marketing Mike Shoemake.
The E suffix to the processor parts indicates the integration of a security engine based on the standalone MPC184/185 security processors. The engine on board the MPC8349E and MPC8541E handles data encryption standard, Advanced Encryption Standard, public-key encryption and secure hashing and digest execution using MD5 or SHA-1. The engine has a dedicated random number generator, and can use the drivers developed for the MPC18x series.
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