Lattice Semiconductor Corporation announced the release of its ispLEVER version 4.0 design tool suite, including major upgrades in performance and features, for the design of in-system programmable FPGA, CPLD, and ispGDX devices.
ispLEVER 4.0 upgrades provide users with the highest device performance yet available, and runtime, improved by over 20%, equals industry leading levels. Users will find enhancements in every area of the design flow that improve design efficiency and ease the design process.
New ispLEVER 4.0 features include TCL script editing and recording, source files in multiple directories, FPGA preference/constraint editor enhancements, nodal control for CPLD design, expanded module generator support, the ispTRACY in-circuit FPGA logic analyzer, revised web-based help/links and DLxConnect gang programming.
"The ispLEVER 4.0 design tools deliver all the performance our customers demand for fast, efficient, accurate designs. The content, quality and stability of this release establish ispLEVER 4.0 as a major upgrade." said Stan Kopec, Lattice vice president of corporate marketing.
Lattice vice president of software Chris Fanning said, "Enhancements to our design flow and support tools provide our customers with a very robust product. ispLEVER 4.0 also provides the platform to support the next generation of three Lattice FPGA families, optimized for low cost, non-volatile operation, and system-level performance."
Industry standard EDA tools included in ispLEVER 4.0
As it has done with previous design tool releases, Lattice will continue to provide the industry's leading EDA tools from Synplicity and Mentor Graphics with the ispLEVER 4.0 design tools suite.
"Lattice is developing several new FPGA architectures that will offer distinct design advantages," said Joe Gianelli, Synplicity Director of Business Development. "When coupled with Synplicity synthesis tools, ispLEVER 4.0 can permit users to quickly and easily achieve unprecedented FPGA device performance."
Simon Bloch, General Manager, Design Creation and Synthesis Division, Mentor Graphics, said, "We have collaborated with Lattice to satisfy the designer's increasingly complex synthesis and simulation requirements. Mentor Graphics design tools are an integral part of the Lattice ispLEVER 4.0 release, enabling design flow and productivity enhancements for our customers targeting new programmable logic devices."
In-circuit FPGA logic analyzer introduced
Lattice's ispLEVER 4.0 software supports design with all Lattice digital programmable logic devices using a single, easy to use interface and design flow. The tools provide design entry, HDL synthesis, verification, device fitting, place & route, programming, and in-system design debug " everything needed to complete a design project in an efficient package. Tool Command Language (TCL) support is now available to help automate routine tasks. ispLEVER 4.0 is also enhanced with several new capabilities that make working with TCL/Tk easier than ever before. Integrated into ispLEVER 4.0 are a context sensitive TCL Editor, a TCL Recorder, and a TCL/Tk command console for running scripts.
ispLEVER 4.0 introduces the ispTRACY in-circuit FPGA verification tool. Small IP modules feed live signal information from internal nodes (i.e., signals not accessible at device pins). This capability can be triggered with any clock source in the user's design, and utilizes on-chip embedded memory blocks to manage trace memory width and depth for one or more FPGAs. This information can then be displayed and manipulated via a user interface similar to a logic analyzer.
ispLEVER 4.0 also incorporates an updated version of the Lattice ispVM System programming software, which includes the DLxConnect gang-programming support interface. With DLxConnect, the user can manage up to eight concurrent device-programming connections from one PC.
Hundreds of enhancements streamline the design process
ispLEVER 4.0 includes hundreds of enhancements that streamline the design process and boost user productivity. For example, users can now store design module source files in multiple locations and link them at compile time, simplifying the design flow for team-based projects. The constraint/preference editor now includes support for nodal constraints for CPLD design (e.g., timing critical paths, optimization process controls, fanin limits, XOR implementation) and logical groupings of commonly selected items.
Many improvements have also been made to the FPGA Floorplanner GUI, including new tools for trace path timing analysis and layer-based editing. ispLEVER 4.0 also includes the Module/IP Manager interface to design with the latest IP cores available from Lattice. New releases such as Serial RapidIO, PCI Express, FIR filter and DDR SDRAM Controllers have been added to the broad selection of cores previously available.
A comprehensive list of ispLEVER 4.0 enhancements may be viewed at:
Availability and pricing
ispLEVER 4.0 design tools are available now in a variety of PC- and UNIX-based configurations. List prices begin at $995.