Santa Clara, Calif. -- PMC-Sierra's RM9150 microprocessor combines the E9000 64-bit MIPS microprocessor core with the new system interconnect called the Fast Device Bus for embedded control processing applications such as Ethernet routers and switches, line cards, network attached storage, industrial control, high-end laser printers, imaging, and high-end consumer applications that require multiple high-speed interconnects and single-chip integration.
The Fast Device Bus interconnect was defined to fully leverage the performance of a 1GHz E9000 processor and support an extensive set of high-throughput peripherals, such as a 200 MHz 64-bit DDR SDRAM controller, a 600 MHz HyperTransport interface, as well as two Gigabit Ethernet MACs, and dual PCI interfaces. "The RM9150 is the first in a family of products designed using PMC-Sierra's Fast Device Bus-based SoC platform," said John Monson, vice president of marketing for the Microprocessor Products division at PMC-Sierra.
The RM9150's E9000 processor and on-chip peripherals are linked to the Fast Device Bus through a common design interface, PMC-Sierra's Generic Device Interface (GDI). GDI is claimed to be a simple, easy-to-design-to interface for new or existing Intellectual Property (IP) blocks to support SoC design flows for standard products, customer specific products, and ASICs. GDI is scalable and interconnect independent, in that any IP designed with a GDI interface is re-usable, and can support either bus or switch architectures. In addition, designing all on-chip peripherals with a GDI interface greatly reduces the design verification time required, and enables seamless IP block integration for better performance and faster time to market.
The E9000 processor can scale from 600 MHz to 1 GHz operating frequencies and supports 256KB of low-latency L2 cache tightly coupled to the processor. This enables the RM9150 to maintain compatibility with and leverage a comprehensive offering of optimized compilers, operating systems, and 3rd-party debug tools support, that are currently available for the RM9000x2 and RM9000x2GL product families.
The RM9150 feature set includes a 64-bit 200 MHz SDRAM controller capable of supporting both DDRI and DDRII memories. Also included are two 10/100/1000 Ethernet controllers, a 600 MHz DDR HyperTransport interface, dual 32-bit, 66 MHz PCI controllers, a 4-channel DMA controller, a Local Bus controller for glueless support of Flash, Compact Flash, PCMCIA, and external USB devices, dual asynchronous receiver/transmitter (DUART), 32KB of scratch memory, and 64 GPIO pins.
Initial samples of the RM9150 device are planned for Q3 2004 with volume pricing estimated at $85 for 600 MHz devices. The RM9150 is fabricated in 130nm CMOS process and is available in an 896-pin Flip Chip BGA package.