It is well know that ASICs can provide the best cost benefit if the situation is right. The definition of 'is the situation right' can be a somewhat gray area, but basically blends volume, cost, time to market, and risk.
That's one reason FPGA technology is so healthy. The ability to take a generic part, use a suite of tools, and create a virtual system on a single chip in your own lab is very appealing. With ASICs, once the design is submitted, everyone waits nervously until parts come in and can be tested.
FPGAs on the other hand, can be tested right away, live and in system. What's more, FPGA designers do not shy away from the iterations loop which allows us to say 'yes, it's working OK but as long as I have the time, I can make it better'.
Then there's the costs. While FPGA tools and parts are not typically cheap, FPGA designs are much more attractive since the NRE to get working parts in our paws is not there.
If volumes are high enough, FPGAs can be turned into ASICs, but, typically they are just hardwired versions of the same FPGA architecture instead of optimized cells that reduce die size. As a result, the time, effort, and expense of a true ASIC can always be more economically palatable.
But, engineers gather no moss and new approaches and techniques can sometimes change everything. We may have that case here with the eASIC announcement of it's fabless semiconductor status.
eASIC has an interesting approach. They come from the IP side where they have been providing the licensable IP core for embedding in System-on-Chip designs. The architecture is an array of embedded configurable logic blocks called eASICores. The logic cells (eCells) use SRAM based LUTs (Look Up Tables) and flip-flops which allow dynamic or power up configuration, just like many of today's RAM base, LUT based FPGAs.
What brings this to a new level is that the eCells are inter-connected by a wiring grid exclusively done on the upper metal layers. This allows a design to be customized by only generating one mask layer which merely consists of vias that do the interconnection.
As a result, while not instant turn around like a desktop FPGA development system, turn around is very fast compared to a full fledged ASIC. What's more, the company states there is no NRE associated with the design and production using this approach. The single Via-customization means that an alternative lithography approach like Direct-write eBeam can be used to eliminate the customization tooling cost, shorten time-to-market and add manufacturing flexibility.
What's a bit more subtle here is what this allows us to do. Instead of using and FPGA and IP processor or peripheral cores, we can now design our own hardwired functionality and put in configurable or reconfigurable logic as we see fit. In other word, instead of fitting something in a box, we are making the box to fit what we want it to.
The company will offer Structured ASIC chips, while continuing to provide Structured ASIC technology. This second phase of their business strategy is being developed in partnership with Flextronics Semiconductor. This Structured ASIC product family will be fabricated with IDM semiconductor company, at 0.13 micron, and is scheduled for production launch in early Q1 2005.