eASIC, a provider of breakthrough Structured ASIC technology and products, and Golden Gate Technology, a developer of power driven physical design tools, today announced the adoption of two products from Golden Gate's GoPower suite. The IC-Plan" and PowerPlacer" tools will be used for eASIC's Structured eASIC array. With this cooperation, the partners will incorporate Golden Gate's clock aware physical design into eASIC's tools set for Structured ASIC, responding to the market requirements of less power consumption, reduced wire length and guaranteed routability. As part of the agreement, two of Golden Gate's products, the advanced power managing floorplanner (IC Plan) and the advanced power reducing placer (PowerPlacer), will be integrated into eAISC's tools kit for designer's use.
'We are excited to have this opportunity with eASIC', said Dr. Michael Burstein, CEO of Golden Gate Technologies. 'Golden Gate's advanced floorplanner and placer work well with the Structured eASIC product family. Our tools will work together with existing eASIC tools at a stage in the flow that has a significant impact on design closure.'
'Golden Gate's physical design tools are very important for addressing today's deep submicron ASIC design challenges,' said Zvi Or-Bach, eASIC President and CEO. 'After evaluating the tools, eASIC was very impressed with the Golden Gate's PowerPlacer quick run-time, reduced wire length and superior routability. We found it is a perfect match for our customer's needs. Using Golden Gate's floorplanner helps us in providing design-friendly Structured ASIC, which is NRE-free, removing design-entry barrier and allowing low-cost and high performance ASIC. This integration of powerful EDA tools and innovative technology allows us to create a comprehensive Structured eASIC offering from RTL to complete physical design.'
Production release of the Structured eASIC tools set is slated for Q4 CY 04.