Actel Corporation announced that the company's flash-based, field-programmable gate arrays (FPGAs) were chosen by Hamilton Sundstrand, a division of United Technologies Corporation, for the F-35 Joint Strike Fighter (JSF) project. Actel's single-chip, reprogrammable ProASIC Plus devices were selected to manage the communication protocol in the fighter's engine control system and to serve as the interface to the engine's central processing unit. The ProASIC Plus family's reprogrammability facilitated rapid prototyping of the new high-speed communication protocol, while its non-volatility and single-chip form factor enabled engineers to meet the system's tight board-space constraints. Hamilton Sundstrand also used Magma Design Automation's PALACE physical synthesis tool for programmable logic devices, available as part of Actel's Libero Integrated Design Environment (IDE), to create a more efficient design and achieve the highest performance for the ProASIC Plus FPGA solutions.
'The combination of reprogrammability and nonvolatility provided by Actel's ProASIC Plus FPGAs was critical in our selection process as we looked for a solution that allowed us to prototype quickly and would also take us through production. Design security and firm-error immunity were also strong considerations in the selection of an FPGA for this design,' said Patrick J. Sears, senior FPGA design engineer, ASIC group, at Hamilton Sundstrand. 'Additionally, we were impressed by PALACE and its ability to improve our overall design performance by as much as 50 percent.'
Ken O'Neill, director, military and aerospace product marketing at Actel, said, 'Hamilton Sundstrand's selection of our APA750 device reinforces our long-standing reputation for delivering reliable, high-performance products for the military and aerospace markets. We look forward to working closely with them on future generations of complex aircraft engine control systems and other products.'
Behrooz Zahiri, director of marketing at Magma Design Automation, said, 'Using our PALACE physical synthesis software, Hamilton Sundstrand not only improved device performance, but also saved significant design time by achieving timing closure with fewer design iterations.'
About ProASIC Plus
The ProASIC Plus family consists of devices ranging from 75,000 to 1 million system gates. The combination of a fine-grained, single-chip ASIC-like architecture and non-volatile flash configuration memory makes Actel's ProASIC Plus offering a strong ASIC alternative. The devices are live at power-up, low-power, highly secure, immune to neutron-induced firm errors, and require no separate configuration memory, all characteristics shared by ASICs. The ProASIC Plus architecture and design methodology support popular FPGA and ASIC tool flows, reducing time-to-market and permitting designers to migrate easily between FPGA and ASIC solutions.