eASIC Corp, a provider of breakthrough Structured ASIC technology and products, announced taping out of its first Structured ASIC array to be fabricated by a European IDM partner at 0.13 micron process technology. The taped-out array called FA1, is the smallest member of the company's Structured eASIC product family. The initial parts will be used to characterize timing and power for the Structured ASIC fabric and cell libraries. The complete product family is scheduled to be released for production in early Q1 2005. This product is being co-developed with Flextronics Semiconductor who will also be offering Structured ASIC products and services. eASIC Corporation, San Jose, CA 95124, USA.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.