There is a wide range of imaging devices that use Low Voltage Differential Signaling (LVDS) standard to transmit serialized RGB data at gigabit rates. EPSON has been supplying LVDS Receiver for many years in applications with focus on liquid crystal panels and home electronic appliances. Taking advantage of such experience EPSON has developed a more worthy and flexible solution: a specific Embedded Array family with LVDS Receiver Macro included. This product line boasts a rich variety of pre-assembled standard masters with different user logic area size (sea of gates) and a set of embedded hard-macros. End-customers can select which master is most suitable for their own needs and customize its user logic area by metal masks, achieving high performance ASICs with low cost and low TAT. Following Macro-cells can optionally be embedded in the LVDS ASIC: Spread Spectrum macro to reduce EMI noise of the CMOS I/F signals; Custom line memory to support 6 to 10 bit per RGB color mapping; Other memories: SRAM, ROM, FIFO, OTP-ROM; Voltage detector for power surveillance; PLL, DLL and self-running oscillator; 32-bit RISC core. Interface: IZC bus, USB FS, UART. Epson Europe GmbH, 80992 Munich, Germany.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.