Lattice Semiconductor Corporation announced its LatticeECP-DSP and LatticeEC FPGA device families, architected to provide the most optimized feature sets combined with the lowest total solution costs of any FPGAs. The new LatticeECP-DSP ("EConomyPlusDSP") products, targeted for high-performance DSP applications, provide up to a 50% performance and 75% logic utilization improvement over other low-cost solutions when implementing common DSP functions. The LatticeEC ("EConomy") FPGA product family, targeted for general-purpose FPGA applications, is a precise and targeted response to the market's explosive demand for low-cost, architecturally streamlined logic solutions.
Through advanced 130nm silicon technology, an optimized architecture and proprietary circuit design, the new Lattice devices lower total solution costs by up to 30% to 50% compared with existing FPGA solutions, and are expected to broaden the adoption of FPGAs within the $20 billion ASIC marketplace.
"These new devices represent the first wave of a new generation of FPGAs from Lattice focused on specific, high-growth FPGA market segments," said Cyrus Tsui, Lattice Chairman and CEO. "LatticeECP-DSP and LatticeEC devices are targeted at the low-cost FPGA segment, which is experiencing explosive growth. We believe these products provide an optimum alignment of low-cost and high-performance that will result in superior products and value for our customers."
LatticeECP-DSP devices (also referred to as LatticeECP devices) and LatticeEC devices are implemented on a cost-effective, production-proven, Low-k, 130nm CMOS process with copper metallization fabricated by Fujitsu Limited. The devices utilize a 1.2 V power supply.
This technology, combined with efficient silicon design, results in very small die sizes while providing the new Lattice FPGAs with the most attractive feature sets in their class.
Lattice has also announced the scheduled availability of comprehensive design tool support for the LatticeECP-DSP and Lattice EC families, and an extensive range of IP cores suited for high-volume applications.
LatticeECP-DSP: High-Performance, Low-Cost sysDSP Capability
The LatticeECP-DSP product family embeds advanced, high-performance sysDSP blocks capable of implementing multiply, accumulate, summation and pipelining functions within a
low-cost FPGA fabric. Each sysDSP block can be programmed to implement one 36x36, four 18x18 or eight 9x9 multipliers. The devices can implement DSP functions up to 10,000 Million Multiply Accumulates per Second (MMAC/S), at costs as low as .5 cents per MMAC/S. This capability is ideal for compute-intensive applications such as image processing and software-defined radio. Other low-cost products either sacrifice DSP support entirely, or provide only basic multiplier support.
"Traditionally, FPGAs have not been widely used to perform DSP functions in cost sensitive, high-volume markets," said Stan Kopec, Lattice vice president of corporate marketing. "Low-cost FPGA devices have either provided no DSP-specific features or provided only basic multiplier support. With the LatticeECP family, our approach has been to provide high-end DSP features in a low-cost FPGA fabric, delivering exceptional performance with uncommon value. We believe this will greatly expand the use of FPGAs in cost sensitive DSP applications."
Designers implement many DSP functions, but the most common ones are filter functions such as Finite Impulse Response (FIR) and Infinite Impulse Response (IIR). Lattice recently benchmarked a 64-tap FIR filter and a 4 th order IIR filter, both operating on 18-bit data. The results showed the performance of the Lattice solution was up to 50% higher, and logic utilization was improved by 75% when compared to other low-cost FPGAs.
LatticeECP-DSP devices will be available in a range of densities between 6K and 41K LUTs. The devices provide I/O counts from 97 to 576 in a variety of low-cost Thin Quad Flat Pack (TQFP), Plastic Quad Flat Pack (PQFP) and Fine Pitch Ball Grid Array fpBGA (1mm) packaging.
LatticeEC Architecture a "Ground Up" Low-Cost Total Solution
From initial planning with customers through architectural definition, design and choice of manufacturing process technology, the LatticeEC was created to be the FPGA with the features system designers agree are essential to high-volume applications, and deliver them at a price that finally makes widespread adoption of high-volume FPGAs economically attractive.
For example, in 1K volumes, published LatticeEC pricing is 20% lower than current low-cost FPGAs that offer similar density and I/O. Traditionally, SRAM-based FPGAs have required expensive, proprietary non-volatile boot PROMs supplied by the FPGA vendor. These devices can account for over 35% of the total FPGA solution cost. Driven to high-volume by a variety of consumer products, SPI Flash memories offer a low-cost, non-volatile configuration option not previously exploited by FPGA vendors. Cost-effective SPI memories now available from third party suppliers can provide a cost per bit 4 times lower than proprietary boot PROMs. In defining its new products to minimize total solution cost, Lattice becomes the first FPGA vendor to provide standard SPI memory configuration support.
All LatticeEC architectural elements such as logic blocks, I/O capabilities including DDR support and embedded memory, among others, were evaluated in the context of their targeted high-volume applications as the devices were defined. The feature sets were then precisely sculpted to be neither excessive (driving up cost) nor "bare bones" (limiting the application range) in order to maximize their broad adoption. The resulting combination of a superior streamlined architecture, compact circuit design and production-proven technology found in the LatticeEC and LatticeECP-DSP devices can reduce total solution costs by up to 30% to 50% when combined with low-cost SPI boot PROM.
LatticeEC devices will be available in a range of densities between 1.5K and 41K LUTs.
The devices also provide I/O counts from 67 to 576 in a variety of low-cost packaging options including TQFP, PQFP and fpBGA, all pinout-compatible with the corresponding LatticeECP-DSP devices.
A Closer Look: Optimized Architecture
Based upon industry-standard, synthesis-friendly 4-input look-up table (LUT) logic blocks.
Only twenty-five percent of the logic blocks contain distributed memory, an optimization that reduces cost while supporting the majority of customers' needs for small amounts of distributed memory.
The availability of sysCLOCK Phase Locked Loops (PLLs) and Embedded Block RAMs (EBRs) allows designers to reduce costs further by integrating these functions within the FPGA, rather than with discrete devices.
Advanced sysI/O buffer capability supports standards such as LVCMOS, LVDS, LVTTL and PCI, as well as SSTL and HSTL, allowing users to easily and efficiently interface to the industry's most popular bus standards. These standards were carefully selected to maximize application range while minimizing die area.
DDR memory has become the low-cost memory of choice: estimates suggest DDR will represent 75% of DRAM bits shipped in 2004, up from 39% in 2002. The Lattice devices have dedicated circuitry to simplify DDR memory interfaces, while providing the highest performance, integration, signal integrity and ease of design for FPGAs in this class.
The Lattice devices can be configured through a variety of methods, including industry-standard SPI Flash memories, as mentioned previously. These readily available devices feature a very small (6mm by 5mm) 8-pin SOIC footprint that reduces configuration device space while providing high-speed program download over their 20MHz serial interfaces.
Design Tools and IP Support
Design support for the LatticeECP-DSP and LatticeEC devices will be provided by the next-generation software suite of design tools, Lattice ispLEVER version 4.1. These ispLEVER design tools will provide designers with access, in one software package, to all Lattice digital devices and include synthesis support from Mentor Graphics and Synplicity.
An extensive range of IP (intellectual property) cores, particularly suited for high-volume applications, will be available from both Lattice and its IP partners. Complete details of IP support will be announced throughout 2004.
Availability and Pricing
Samples of the first devices, the 20K LUT ECP-DSP20 and EC20, are expected to be available in July 2004 with the remainder of the densities expected to sample during 004.These devices feature 424Kbits of Embedded Block RAM and either 360 (484 fpBGA) or 400 (672 fpBGA) general-purpose I/O pins. The ECP-DSP20 also features 7 sysDSP blocks capable of implementing up to twenty-eight 18x18 multipliers.
Published prices in 1K quantities for the ECP-DSP20 and EC20 in the 484 fpBGA package are $59 and $49, respectively, 20% lower than competitive published prices.