Zarlink has expanded its portfolio of timing and synchronization devices with two digital PLLs that deliver industry leading jitter performance and superior features to ensure the reliable transport of data, multimedia and voice traffic. Combining enhanced features such as flexible reference monitoring and superior holdover capabilities with jitter performance of less than 0.5ns " several times better than competing devices " the ZL30100/1 digital PLLs easily and cost-effectively meet Stratum 3 and Stratum 4/4E requirements for access, edge, and customer premises equipment. The ZL30101 digital PLL is well suited for central office and edge equipment requiring Stratum 3 timing, such as master DSLAMs (digital subscriber line access multiplexers) powering consumer broadband access. Central office equipment extracts its timing information from dedicated synchronization references. The holdover capability of the premier ZL30101 timing chip allows externally timed network equipment to receive and send data even when the network synchronization source is temporarily lost or interrupted. This ensures there is no service disruption for subscribers. In comparison, line-timed customer premises and access equipment, including VoIP Gateways that support enterprise communications services, extracts its timing information from the same T1/E1 trunk lines that carry data. Line-timed equipment requires highly reliable clocks synchronized with Central Office equipment to ensure the proper flow of data, multimedia and voice traffic between emerging and legacy networks. The ZL30100 digital PLL allows designers to cost-effectively design a timing solution meeting Stratum 4/4E requirements for a range of line-timed equipment - from PBXs (private branch exchanges) and remote access DSLAMs, to wireless base stations, enterprise routers and gateways. The device provides clocks meeting international standards during normal operation, and enhanced reference monitoring and reference switching capabilities that allow the PLL to switch the source of timing from a failed interface to an operational interface without losing data. Zarlink Semiconductor, 91944 Les Ulis Cedex A, France.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.