Design teams all over are debating. While time to market and risk can be substantially lowered by going the FPGA route, the ASIC path carries potential benefits that can't be ignored. An ASIC implementation can for the most part, always map functions and logical blocks more efficiently that those implemented in generic logic granules. The ultimate attainable performance can be higher with a custom tailored implementation on an ASIC. And, if every 't' is crossed and every 'i' is dotted, the cost for an end product can be substantially lowered.
But, FPGAs allow the same product to be updated more easily. If there are any mistakes, or even better ways to implement a design after the initial product release, it simply means a new 'fusemap' code to upgrade the functionality or performance. This can also be beneficial say if an early flavor of a design implements an emerging standard. As the standard is improved or embellished, it can be easier in an FPGA to upgrade the functionality.
As of late, there have been some hybrid approaches that provide designers with very low risk, fast turnaround ASICs, and even some that provide a structured ASIC with programmable functionality. Of course, when an embedded micro is put on an ASIC or and FPGA, this is always possible.
What I mean is the ability to spin an ASIC that has programmable logic functionality spun into it. It's always been possible to design logic to be programmable, but this can be tedious, introduce space and cost penalties, and add a layer of complexity to what is often already a complex design.
That's why I like to keep tabs on new or cross-pollinated approaches. One such approach comes from Leopard Logic, who has just qualified what they call a CLD for Configurable Logic Device. These are simpler to customize than an ASIC but retain the programmable nature of FPGAs to try and provide the best of both worlds.
What Leopard has come up with is a new architecture that
resembles both an ASIC and an FPGA. The Gladiator as it is called, is 100% user programmable and you can perform instant design changes as with FPGAs. But, for critical functions that need to be small and fast, fixed blocks can live happily on the chip.
HyperBlox FP fabric cells based on SRAM, can be reprogrammed by the user anytime. The HyperBlox MP fabric uses the identical logic cell architecture, but replaces the SRAM configuration with a single-layer mask configuration to achieve significantly higher density, increased performance and lower power consumption. This provides a low risk, higher performance migration path upgrade once the captured design is verified to satisfaction.
Based on a fully hierarchical, directly buffered,
point-to-point interconnect scheme, Gladiator exhibits deterministic predictability and reliability. Performance up to 500MHz is attainable and power dissipation of less than 6 watts is typical of the CLD6400 part which houses 6.4M system gates, 2.3Mb of on-chip memory, MACs and PLLs/DLLs.
With 32 GMAC/second DSP throughput and 16 on-chip PLLs and DLLs to drive global clocks and implement high-speed interfaces, the devices are ideally suited for high-speed signal processing and communications applications.
The design flow utilizes industry standard tools from Synopsys, Mentor Graphics, and Accelchip. Leopard also has their own tools; the unified ToolBlox design environment which supports rapid timing closure at the designer's desktop.
What they have just announced is the successfully completed functional testing and qualification for important parameters. This verification lets them plug in the back end numbers to provide the detailed timing analysis with confidence since they have correlation of the timing libraries to the actual silicon performance.
Manufactured in TSMC's 0.13 CMOS process on 300mm wafers, the Gladiator CLD6400 touts low power, fast turnaround time, and the 'lowest' total-cost-of-ownership for production volumes between 1,000 to 100,000 units. (Note these are moving target numbers which are subjective at best).
But, all in all, the architecture and approach opens new avenues which addresses the low risk platforms with fast development times and low unit and NRE costs. First production shipments to customers are scheduled for delivery for Q3, 2004.