Since product-term architectures, embodied by CPLDs, and Look-up Table (LUT) based-architectures, embodied by FPGAs, have existed designers have been trying to determine which architecture is best suited for a given application.
Each approach certainly has its merits. Product-term-based architectures provide across chip pin-to-pin delays as low as 2.5ns, while LUT-based architectures have remained in the 4 to 5 ns range. LUT-based architectures, on the other hand, demonstrate good on-chip register-to-register performance, typically referred to as FMAX, especially for higher capacity designs. Product-term architectures typically offer the lowest cost implementation at densities up to 256 macrocells (approximately 500 LUTs). High-volume pricing for low-density product-term devices starts at well below $1.00. At higher densities, the efficiency of the segmented routing associated with the LUT-based approach allows these devices to provide lower cost.
Many factors influence which architecture is best suited for a given application. However, in many cases the broad category of logic class is a pragmatic way to approach the decision. There are several ways to classify logic, but one most relevant to selecting an architecture is to view applications as falling generally into one of three categories: control, bridging and interfacing, and data path.
Control: This includes applications such as decode logic, data and clock muxing, simple state machines and power-up logic. Typically, these applications require fast pin-to-pin performance because a decision about the next action has to be made before the next clock cycle. It is also common to find requirements for low skew in this application space. The size of these designs tends to be relatively small, most typically below 256 macrocells. This combination of requirements tends to favor a product-term-based solution.
Bridging and Interface: This includes bus-to-bus interfaces, bus interfacing and memory interfacing. Classic examples of these applications would be PCI bus interfacing and memory controllers. In this space, pin-to-pin timing remains tight, which tends to favor the product-term approach. Depending on the nature of the bridge being constructed, there may be sufficient internal logic to favor the higher-density cost efficiency and FMAX performance of a LUT-based approach. A designer choosing this path can expect some challenges in meeting I/O performance needs. Another factor influencing component selection here is the requirement for on-chip memory to implement small FIFOs and mailboxes. If required, these tend to favor those LUT- and product-term-based architectures that provide these capabilities.
Datapath: Here a design implements a large complex function based on the input data in order to create the output datastream. Good examples of these applications include DSP functions, complex bridging applications and video processing. Typically, the pin-to-pin speed is not critical in these applications, but the overall throughput determined by FMAX is. The complexity of these applications is such that they most often represent 2000 LUTs or more. For these applications, the LUT-based architecture almost always provides the best solution