Most designers are paying close attention to design-for-test (DFT) these days. In fact, for many EEs, DFT using boundary-scan is a design imperative. With the IEEE-1149.1 Standard Test Access Port and Boundary-Scan Architecture setting the standard, vendors are dishing up a bevy of innovative 1149.1 hardware and software tools.
By Alex Mendelsohn, eeProductCenter Senior Technical Editor
Testability at both chip and board levels continues to be a concern to designers, rearing its head during design, production/manufacturing, and in the field. Woe to the designer that finds that a product is un-testable.
The situation is exacerbated as physical access to test points disappear in densely packed and multi-layer circuit boards. Indeed, some boards are so dense and complex that if test coverage isn't designed-in from the get-go, adequate test coverage is well nigh impossible.
The Silicon Quandary
The quandary of testability also exists in highly dense chips. "Although the idea of DFT largely focuses on board design and board manufacturing, boundary scan is one of the most common and important parts of production testing of chips, too," observes Haggai Bar-Shalom, a test engineer at Metalink (Yakum, Israel).
"But, the same patterns used to generate board testing can be used in IC production testing to test TAP (test access point) and boundary scan functions," observes Bar-Shalom.
The IEEE-1149.1 boundary scan spec, dubbed the Standard Test Access Port and Boundary-Scan Architecture, sets the standard. It defines a 4-wire or 5-wire electrical interface and a control protocol to communicate with a target.
The immediate benefit of boundary-scan for digital testing is typically a reduction in the number of test probes on a bed-of-nails fixture as used in ATE (automatic test equipment). Probe-count reduction equates to lower fixture costs, as well as simpler board designs and greater test coverage. In addition, boundary-scan delivers in-site programming---with high throughput---for chips such as flash memories and CPLDs.
A host of companies support the IEEE spec. One of these, Corelis (Cerritos, Calif.), offers a less-than-$6000 controller. Its NetUSB-1149.1/E is an intelligent boundary-scan controller that can be connected to your PC either across a high-speed Universal Serial Bus (USB 2.0) connection, or across a 10/100Base-T Ethernet local area network.
Using this controller, your desktop or laptop can be used for boundary-scan testing---in all phases of a product's life cycle, including design, manufacturing, and field service. To speed the process, the NetUSB-1149.1/E ships with built-in self-test (BIST) software and Plug-and-Play device drivers for use with all versions of Windows.
The NetUSB-1149.1/E can be used for testing as well as in-system programming of CPLDs, FPGAs, and flash, on up to four concurrent (ganged) JTAG chains. It can deliver test vectors at a sustained TCK (test clock) frequency of 80 MHz on all four JTAG chains. It does this while simultaneously verifying results in hardware at each individual TAP.
Corelis supports its product with a test program generator called ScanPlusTPG. Boundary-scan test vectors developed with ScanPlusTPG can be executed directly on the NetUSB-1149.1/E.
The system's 480-Mbit/s USB or Ethernet connectivity means you can use this intelligent tester either on your bench or remotely---even across the Internet. It should be easy to link the factory floor with your lab or with your QC/QA department. "By having a common test platform for both design and manufacturing you can realize tremendous costs savings," claims Jim Rodgers, Technical Marketing Engineer at Corelis.
In use, the controller can apply test vectors and/or in-system programming (ISP) patterns, using various JTAG chain topologies. It gives you a hardware comparison of expected patterns against observed results.
Finally, the NetUSB-1149.1/E also packs A/D converters that can measure voltages on your target. Voltages from two distinct levels can be compared against user-defined limits to give you signal voltage checks at any stage of a test plan.
The TAPs also have a dedicated pin on the JTAG connectors. This pin can be used to detect the presence of a target board as well as the proper insertion of test cables.
That's a useful feature that should go a long way to ensure ease of use---especially in production line settings.
Corelis also offers JTAG controllers that work using a PC's parallel port. For example, the company's intelligent PIO-1149.1/E controller supports two boundary-scan chains, using four I/O pins that can be configured individually through software as inputs, outputs, or open-collector drivers. This product also lets you configure signal lines of your own definition in order to test non-boundary-scan areas of your design.
USB's Mighty Mouse
Speaking of USB-equipped JTAG controllers, one of the coolest USB-connected new products was recently rolled out at Macraigor Systems (Brookline Village, Mass.). Known for its on-chip debug (OCD) technology (affectionately referred to as the OC Demon), Macraigor offers a full-speed USB controller that implements IEEE-1149.1 as well as BDM (background debug mode).
Macraigor's $750 ultra-small board, dubbed the usbSprite, packs a high-performance interface. And, its API (applications programming interface) is compatible with popular software debuggers, including the GNU tool suite (GCC, GAS and GDB).
The hardware module itself measures just over an inch square and connects to a host system via a miniature USB connector. That's significant because most new laptops ship without parallel ports.
Based on Macraigor's proprietary OCD technology, the usbSprite operates as a converter of JTAG commands. A Windows host PC communicates with it using USB's protocol to route OCD signals required by a target. The host port can be JTAG, MIPS Technologies' E-JTAG, BDM or any of several other types of connections. OCD Commander, an assembly-level software debugger, and a GNU tools suite, are available at no charge from Macraigor's Web site.
According to Craig Haller, Chief Engineer at Macraigor Systems, the usbSprite will change the way end users will look at debug connections. "There's no need for dealing with JTAG headers or non-standard connectors," says Haller. "USB lets you use cables up to sixteen feet in length, too."
As an example of the usbSprite's performance, Haller says binary files can be downloaded to an Xscale target at 180-kbytes/s, and to an MPC88560 at up to 250-Kkytes/s. "With higher clock speeds," says Haller, "information is transmitted and received from the target board more efficiently for setting breakpoints, single stepping, tracing, and for diagnosing problems and other target communications."
Another company offering a low cost controller (although a bit more than Macraigor's $750 product) is JTAG Technologies (Stevensville, Maryland). Its controller, selling for about $4000, has selectable USB 2.0, Ethernet, and FireWire interfaces.
JTAG Tech's DataBlaster JT 37x7/TSI (Triple-Serial Interface) unit essentially lets you do JTAG testing on-the-move, thanks to the choice of USB 2.0 (as well as USB 1.1), Ethernet, and FireWire interfaces. You pick what best suits the environment you're working in at the moment or location.
Performance-wise, a DataBlaster JT 37x7/TSI offers sustained test clock speeds of up to 40 MHz, and has a flash image buffer memory that can be expanded up to 128 Mbits in size. The system comprises four synchronized TAPs that are able to support multi-TAP test targets, or gang programming of four single TAP targets. High-speed signal conditioning, logic threshold adjustments, and cable delay compensation is handled by a special extension module.
JTAG Tech actually supplies three versions of the DataBlaster. The JT 3707 model is for board testing, CPLD programming, and flash programming of small data blocks. Significantly, it can be upgraded to a higher performance JT 3717 by adding what the company calls an Enhanced Throughput Technology (ETT) module.
The JT 3717 is for design debugging as well as in-system programming of CPLDs and moderately-sized flash memories, as well as for board testing during high-volume manufacturing. This product packs 64-Mbits of on-board image memory.
The JT3717 also is upgradeable; it can be can be re-vamped to a JT 3727 by adding a flash image module. Like its smaller counterparts, a JT 3727 is for in-system programming of flash arrays and CPLDs, as well as for board test and debug, but it packs 128 Mbits of flash image memory. As such, it lends itself to flash applications in small-volume as well as large-volume production settings.
Regardless of which you choose, all JT 37x7 products support programming of flash widths from one bit to more than 64-kbits. However, an image counter, comprised of two separate counters for source and destination, also permits a block of image memory data to be positioned anywhere in target memory.
All DataBlasters also support the company's AutoWrite feature. JTAG Tech claims that it can shorten flash programming time by a factor of 2x to 3x, using realtime hardware control of flash's WE (Write Enable) line, instead of via the boundary-scan chain.
Finally, the DataBlasters also support flash-specific control signals, including Vpp Enable (to control optional programming voltages on the target), User0/User1 (user-definable, software-controlled), and Ready/Busy (for optional use to verify completion of an operation).
A Product For Chip Test
For chip test, JTAG Tech also offers its new BSDL Verification/Creation System. It automatically extracts a boundary-scan structure from a chip to create a BSDL (boundary scan description language) file. Or, if a BSDL file already exists, it verifies its accuracy compared with the device.
The resulting BSDL file describes the boundary-scan characteristics of the device, including scan register length, ID code (if present), instruction codes, and I/O lists.
Since the BSDL Verification System doesn't require detailed knowledge of IEEE-1149.1, it's relatively easy to use. Personnel in engineering and quality departments, IC developers and ASIC design groups, as well as test engineering departments, can likely shorten time-to-market and produce error-free BSDL files by using it.
The BSDL Verification System consists of BSDL Verifier/Creation software, a BSDL512 hardware unit (it supports 512 I/O channels), and a JT 3707 controller.
In use, the company claims the system will automatically generate a 100-percent accurate BSDL file, in compliance with 1149.1, that precisely corresponds to the boundary-scan logic implementation within the chip. In addition to this capability, it validates an already existing BSDL file against an actual device.
What About Analog?
JTAG Technologies also has a product called the JTAG-1149.4 Explorer that lets you exploit analog boundary-scan in accordance with the IEEE-1149.4 group's recently published standard for extending boundary-scan testability to mixed-signal and purely analog chips.
Defined formally as The Mixed Signal Test Bus, the standard defines access to the analog pins of a mixed-signal device in order to drive out digital stimuli and sense digital responses. It's also defined as a means to drive analog stimuli and sense analog responses.
The Mixed Signal Test Bus standard also facilitates 1149.1-controlled test access to components on densely populated mixed-signal boards. It does this by means of a two-wire analog bus. However, for an IC to be compliant with the standard, on-chip analog access must be provided to every analog pin of the chip, and 1149.1 boundary scan must be provided for every signal pin.
An analog mode also permits ac and dc currents or voltages to be routed from extra device pins, to an output analog boundary module (ABM), and to a connected analog device or devices. Analog responses arriving at an input ABM can be routed to extra device pins, and through other devices to external measurement units. In this way, the presence, orientation, and bonding of on-board analog components can be detected.
National Semiconductor (South Portland, Maine), and LogicVision (San Jose, Calif), a maker of embedded test systems for chips and systems, actually offer a general-purpose IEEE-1149.4-compliant IC. It uses LogicVision's embedded test circuitry to provide analog access to board-level circuit nodes.
Back to JTAG Technologies. Implementing the standard, the firm's product comprises a mixed-signal evaluation board with 1149.4-compliant devices, and a separate analog instrumentation module. Armed with that, you can measure passive component values, analog voltages, and transfer functions---on the eval board, or on your own board---all via a boundary-scan TAP port.
Analog isn't the only direction product development is taking at JTAG Tech. One of the latest developments at the company is expansion of the compatibility range for its existing boundary-scan tools. The thrust is to cover all of Agilent Technologies's 3070 Series in-circuit test (ICT) systems equipped with Ethernet ports.
When first announced, JTAG's Symphony product for the 3070 added boundary-scan to certain vintages of the 3070, including UNIX- and Windows-based spins. That capability is now broadened further; every installed 3070 system can now be upgraded for boundary-scan, and Agilent 3070 users can continue using current UNIX operating systems or convert to Windows.
The upgrade is accommodated using JTAG's aforementioned TSI model as shipped with the DataBlasters. Once upgraded, structural tests of the digital portions of units under test can be conducted via boundary-scan, often with pinpoint diagnostic accuracy, using verification patterns generated on JTAG Technologies' development tools.
For More Information
Corelis Inc., 12607 Hiddencreek Way, Cerritos, Calif. 90703-2146. Phone: (562) 926-6727. Fax: (562) 404-6196.
JTAG Technologies Inc., 1006 Butterworth Ct., Stevensville Maryland 21666. Phone : (Toll Free) 877-FOR-JTAG. Fax : (410) 604-2109.
Macraigor Systems LLC, PO Box 471008, Brookline Village, Mass. 02445.