Both advanced and simple system designers share common goals. To create a streamlined design solution that more than satisfies the requirements. Other often critical constraints include size, power, performance speed, durability, and let's not forget cost.
What we want, and what we get are often quite different. Sometimes it's our fault. Our initial concepts need refinement since we are at the beginning of the learning curve. Other times, we are ahead of what's feasible, or, possible with the limited resources, budgets, and times allotted to complete a design.
Either way, as engineers, we know there is always room for improvement and optimization, given just a bit more time. But, time is a key issue.
There is saying that you can tell the difference between and engineering driven company and a marketing driven company. An engineering driven company has superior technology, but, never releases a product since they know they can make it better with a bit more time. A marketing driven company on the other hand, introduces whatever works, even if far from optimal or refined.
Any designer is somewhere between these extremes. But, what changes equations are technology alternatives that re-arrange what's possible, feasible, and doable. Stacking and packing is one of these areas.
A Cross Sectional Approach
To examine what are the trends, visions, capabilities, and limitations of today's integration technologies, I decided to query key companies in several areas of technology. This cross sectional approach ensures that issues and solutions unique to different technology cultures are addressed. For example, makers of Flash will have different integration concerns than makers of SRAM.
I also queried companies that specialize in higher density solutions to see what challenges they face, either real, or, perceived.
Note, marketing is marketing. Several companies' say we are the world's biggest, or largest. If you qualify what the are saying, 'we are the largest maker of blue widgets that fit into this sub specific category', then maybe you can agree they are all right. But, I'm a firm believer that statistics can be made to convey any point, even if the opposite is really true. So take claims at face value.
Monolithic vs Monosystic
The emphasis today for System On a Chip (SOC) is widespread these days. Many key players offer solutions with standard products as well as semicustom or full custom services to address this. In many cases, this is an effective technology, but in many cases it is not.
The true monolithic solution can be the ideal. For the majority of simple applications, this works, but when you move up the complexity wedge, it begins to fall short (see Fig. 1).
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Conversely, monosystic (where a more complex system is created in a single packaged device) has more advanced capabilities, but is feasible to a fewer number of applications and designers.
Note, I make the differentiation between monolithic as being fabricated entirely on a single die, as opposed to monosystic, where multiple die or even components are combined into a single packaged device. Monosystic solutions include System In Package (SIP), Multi-Chip Modules (MCM), and stacked technology.
None of these are really new ideas. But, what is changing is the foundation technology that makes them usable. What's also changing are the demands from the design community.
Low down on the complexity wedge are single chip microcontrollers with embedded peripherals and memory, PLDs, CPLDs, or small FPGAs. These address the needs of the largest swath of applications. Fabrication process advancements have made it possible to put enough resources in a small enough space to appeal to a large enough audience.
But, there are down sides to everything. Smaller geometry's are great for the digital designers, but not the best thing for linear. Resolution is better with larger fabrication geometry's. Noise is lower with larger fabrication geometry's.
As a result, a mixed signal design may actually work better on an older, larger fabrication process. An example of this was AMI semiconductor who offered a mixed feature size ASIC solution. The digital feature size was small, whereas the linear feature size was large. This gave good linear performance and faster, denser digital functionality.
Mixed signal is not the only area where monolithic limitation become the brick wall. Memory is a key area that makes monolithic an infeasable approach.
Thanks For The Memory
A continuing trend is that the makers of microcontrollers, DSP devices and CPLD/FPGAs are giving us more an more memory embedded on chip. This isn't just SRAM either since a lions share of single chip micros house Flash and some even also hold EEPROM.
The memory integration is key in achieving an optimum design and micro makers have done a great job in giving us more capability for the same space and cost. The problem is, we need more, we need faster, and we need denser to tackle the more sophisticated and cutting edge designs higher up the complexity wedge.
It's not just a die size issue that throttles back denser memory for single chip solutions. It's also a process technology issue. Many of the DRAM and Flash processes are very different than plain vanilla CMOS fabrication. These processes are optimized for the specific characteristics that give these advanced and high speed memories their edge.
This is where SIP, MCM, and Stacked technology comes into play.
One key trend has been made clear from all the semiconductor and packaging specialists companies I've spoken to. That is; more end customers are opting to do MCM and/or stacked solutions themselves. They are not completely satisfied with the industries attempt to create standard product to fit their needs. As such, they are undertaking the task of managing and outsourcing the expertise they need to integrate their own ideal solution.
This is good news for more than just the design community. First, semiconductor manufacturers are selling more die level product targeted at MCM or stacked designs. Second, a new service industry is emerging which harnesses specific expertise needed to integrate custom packaged systems. Third, CAE tool makers now have a new market to address with specialized tools.
A couple of things to be aware of when venturing into this new territory for most. Die is not as fully tested as are packaged parts. The semi guys (and gals) put it this way. 'Die level product CAN be fully tested'. Everyone I spoke to reluctantly agreed that packaged parts are always more thoroughly tested that die product.
Another pitfall is that the semiconductor industry has yet to address standardizing die which will be used in stacked or MCM designs. The semi folks are selling existing die without any modification. It is users responsibility to work around some of the issues that could be solved if the standards were in place.
Let's use memory as an example since it is so needed across the board. Modern high speed and dense memory die have among other issues, power and heat concerns. When individually packaged, regular heat dissipating techniques can easily be employed. But, in MCMs and especially in stacked designs, this heat becomes cumulative and more of a concern.
If a standard existed which allowed the semi folks to reduce the drive strength of the I/O buffers for example, a lot of power could be saved and heat reduced. After all, the end device may not have to drive long copper traces as would separate discrete memory devices.
If the entire system was housed in a single package, memory would not have to drive such distances and could reduce it's current, power, and heat. A single standard memory interface layer and a standard pinnout arrangement could be used to seamlessly integrate a mix and match type of memory architecture. The standardized pinnout arrangements are particularly important when mixing memory technologies. Existing JEDEC standards for example have historically shown benefit to the design community.
Another issue yet to be solved adequately is design and development tools. Every semi company and packaging company I spoke with agreed that the development tools have not kept pace with engineers needs. In all fairness to tool manufacturing, there is virtually no standardization on MCM, SIP, and stacked design methodology or materials.
For example, printed circuit board technology is well characterized and parameterized. Simulation tools today can model and reflect the physical effects of transmission lines, termination's, and impedance's. Phenolic materials and dielectric characteristics are fairly universal and well understood.
MCMs, SIP, and stacked technology are not yet this homogenized. The technology is advancing rather rapidly and characterization has not caught up for the tool makers.
For example, Multi Chip Modules have been around for several decades. Early devices were costly and tricky to make because high temperature ceramic substrates were needed along with high temperature conductors like tungsten, to be able to handle the hot annealing process that makes the mini circuit board like ceramic carriers.
Modern techniques use lower temperature substrates and conductors that can be flash annealed to survive intact. This lowers cost, increases yield, makes the finished devices tougher and more robust, and opens up this technology for a larger potential audience.
While semiconductor makers are touting successes in copper based interconnect and lead free process technologies, CAE tool makers have yet to capture the essence of these processes attributes. As such, it's designer beware. You can easily do functional verification, but precision parametric timing analysis is in your court to figure out how to do.
Markets Pushing Transparency
It is the killer applications that usually advance a state of the art. This is true here as well.
Many of the companies I've spoken to, already offer stacked or MCM solutions as standard product. This is mostly true in the memory arena.
For example, when monolithic 1 Gbit NAND Flash devices became real, stacking in a single package gave a head start to those who needed 2 Gbits. Now with 4 and 8 Gbit monolithics emerging, the stacking is allowing virtually the same footprint to house 16 and 32 Gbit single packaged parts (many are focusing on stack sizes of 4 to 6 as feasible today).
The cell phone industry is the key market that is pushing stacked and MCM 'standard' product. It's true that these very large design wins depend on low cost, but, the device makers are striving to not price penalize customers who buy stacked or MCM single chip parts.
That's all well and good, but, let's face it. If costs to make are higher, cost to use are higher still. But, the more the markets drive this technology, the more cost effective it will be.
Where Do We Go From Here
It is clear that there are benefits and potential cost saving associated with a successful System In a Package, Multi-Chip Module, or stacked die/packaging. It should also be clear that there are potential pitfalls along the way.
The simplest approach is to integrate a key area, like memory into a single package. While a good way to partition and save space, the real saving occur when a more system level integration takes place.
You are not alone or inventing the wheel for the first time if you are looking at any of these technologies. Knowledgeable semi folks as well as third party houses have expertise you can tap. There are also good web sites which are central locations for Systems on a Chip vendors.
Once through the process a first time, it won't seem so bad as long as you've been careful. Good luck....
Many thanks to the fine folks at Samsung, SST, IDT, NEC, Tessera, Inapac, Toshiba, Staktek, and Fujitsu for their interviews, photos, and insights.