PLDApplications announced that its PCI Express IP Core coupled with its XpressBridge board successfully passed the complete suite of PCI-SIG compliance tests. PLDA's PCI Express IP Core is designed for ASIC and FPGA technologies, incorporates the Transaction Layer, Data Link Layer, and Physical layers of the PCI Express protocol, and is configurable as an Endpoint, Bridge, and Rootport. Having passed the PCI-SIG suite of tests ensures designers that PLDA's Core meets rigorous industry standards, which minimizes the integration risk and reduces the time to market.
PLDA's PCI Express IP Core passed both stages of the PCI-SIG compliance workshop, a requirement for inclusion on the PCI Express Integrators list. PCI-SIG's Gold Suite test ensures that a product meets all specification requirements, including verification of signal quality, proper implementation of the PCI Express protocol, and examination of the Configuration space.
Interoperability testing, the second stage of the workshop, ensures that PLDA's PCI Express IP Core functions properly with production-ready products from the vendors (such as motherboards, servers, analyzers, and switches). Please visit:
http://www.plda.com/press/pci_sig_compliant.php for more details.
"Today's test results confirm the quality of the solutions we offer," explained Arnaud Schleich, co-founder and Vice President of PLDA. "The Core architecture is based on a kernel design that permits a variety of customers to use the same product in either ASIC or FPGA environments, configured as an Endpoint, Bridge, or Rootport. Customers benefit directly from this approach. Not only does it allow us to offer highly competitive prices, but customers can significantly reduce time to market by using the same IP Core in various products and in different phases of a product's evolution."
PLDA's PCI Express IP Core offers extensive flexibility while maintaining a robust feature set. The Core is configurable with the included Wizard, which enables customers to easily configure the Core as a x1, x4, or x8 Lane, and with up to eight Virtual Channels (VCs). The Core is optimized for a particular technology at configuration time, with specific modules such as memory, pipelining, and latency tailored for either ASIC or FPGA chips.
PCI-SIG compliance also confirms PLDA's three-tiered validation methodology. Functional Core verification is based on testing environments developed by third-party specialists (nSys and Denali), functional PHY verification is performed internally with PLDA's proprietary testbench, and hardware verification is completed with PLDA's XpressBridge board coupled with motherboards from various vendors. Third party PHY IPs and chips are also integrated and tested.