Actel Corporation today announced that its Libero Integrated Design Environment (IDE) offers strengthened support for the company's antifuse-based, single-chip Axcelerator field-programmable gate arrays (FPGAs), extending significant improvements in silicon performance, quality of results (QoR) and timing closure to its Axcelerator customers.
Advancements made within timing-driven place and route, including a new predictive layout and routing technique that allows improved analysis of chip resources, result in an average of 10 percent improvement in Fmax and up to 15 percent improvement on the most complex designs. Additionally, enhancements made to the Mentor Graphics LeonardoSpectrum and Precision RTL Synthesis tools, accessible through Actel's Libero IDE, provide a 14 percent QoR improvement, as well as enhanced global clock buffering, register replication and timing correlation for the Axcelerator devices.
"While the performance, power, cost and enhanced security of our Axcelerator FPGAs continues unrivaled in the industry, working with industry leaders to develop a best-in-class tool suite has allowed Actel to reach unprecedented levels of design capacity for the family," said Saloni Howard-Sarin, director of antifuse and tools marketing at Actel.
"Indeed, with support from our EDA partners, such as Mentor Graphics, and our own commitment to innovation, Actel can assure that with the latest version of Libero, Axcelerator customers will reap increased device potential for their next-generation designs."
Simon Bloch, general manager, design creation and synthesis division at Mentor Graphics, commented, "Actel's Axcelerator devices offer a unique combination of high density, excellent performance and low power. Mentor Graphics has enhanced and optimized Axcelerator support in our LeonardoSpectrum and Precision RTL Synthesis tools, enabling designers to easily leverage these advanced solutions to create and synthesize complex designs using Actel's FPGAs."
Actel's Libero IDE implements a new predictive layout and routing technique that works with feedback on path slacks, allowing customers to significantly improve the performance and routability of their designs. The Libero IDE also offers the latest and best-in-class tools from EDA partners Mentor Graphics, SynaptiCAD, Synplicity and Magma Design Automation, as well as custom-developed tools from Actel integrated into a single FPGA development package. Actel offers one-stop shopping for its customers' EDA tool needs by means of a powerful design manager that keeps track of design files and seamlessly manages the interoperability issues that typically arise when using tools from different vendors. The Libero tool suite also supports mixed-mode design entry input, giving designers the choice of mixing either high-level VHDL or Verilog HDL language blocks with schematic modules within a design.
Pricing and Availability
The Actel Libero IDE is available in three editions: Platinum, Gold and Silver. The Platinum version sells for $2495. The Gold version sells for $595 and the Silver version is available for free. All are one-year renewable licenses. For further information about pricing and availability, please contact Actel.
About the Axcelerator Device Family
Built upon the company's AX architecture, the antifuse-based Axcelerator family delivers better than 500 MHz internal operation and up to 100 percent resource utilization. Additionally, the company's live at power-up, single-chip Axcelerator FPGAs avoid in-rush current spikes, simplify system power supply design and generally offer lower standby and dynamic power consumption than competing solutions. The devices offer levels of design security beyond SRAM-based offerings and conventional ASIC solutions, enabling designers to safeguard against common security problems, including overbuilding, cloning, reverse engineering and denial of service. Because the antifuse configuration cannot be altered once programmed, Axcelerator FPGAs are also not susceptible to firm errors, which occur when high-energy neutrons generated in the upper atmosphere strike the configured cell of an SRAM-based FPGA.