Celoxica announced design flow development through the Synopsys in-Sync program. This development formalizes the interoperability between Celoxica's Agility Compiler and DK Design Suite with the Design Compiler synthesis solution from Synopsys, Inc.
Celoxica's design tools for system level co-design and the rapid development of custom intellectual property cores from C-algorithms, enable designers to retain their single source C files through design exploration, verification and implementation. Celoxica's ESL approach provides the capability for the automatic generation and synthesis of
IEEE compliant RT level VHDL, Verilog and FPGA netlists from ANSI-C or SystemC algorithmic descriptions.
"Celoxica's tools have become a distinctive part of the ASIC/ SoC design flow, now that it connects to the leading hardware implementation flow," said Jeff Jussel, vice president of Marketing for Celoxica. "Linking the Celoxica ESL tools to Synopsys' Design Compiler tools is an important step in realizing the full potential of ESL design."
The development and verification of tool interoperability is being managed through the Synopsys in-Sync program. The initial focus is the optimization of RTL generated from Celoxica's tools for Design Compiler tools.
"For years Synopsys has initiated programs of its own and worked with standards bodies and industry organizations to advance tool interoperability throughout the electronic design automation industry," said Karen Bartleson, director of Interoperability at Synopsys, Inc. "Through the in-Sync interoperability program, Synopsys enables EDA vendors to identify and implement interoperable design flows that maximize the productivity of our mutual customers."