San Mateo, Calif. - Considerations like cost and yield have kept a lot of MCU vendors from rushing into 130-or 90-nanometer processes. Three companies, however-NEC, Fujitsu and Philips-are hoping to avoid the standard 90-nm pitfalls by launching pointed attacks at this potentially lucrative market.
The whole idea of 90-nm processes poses a problem for microcontroller makers. On the one hand there is the inexorable migration toward finer geometries. Stepping off the moving sidewalk to say "this geometry is sufficient" is tantamount to forgoing a promotion because one already earns enough money. It's just not done-in part because of the difficulty of getting back on the moving sidewalk afterwards.
On the other hand, as process geometries shrink, designs get much more expensive and uncertain. Yields become less certain, too. And the cost benefits that are supposed to accrue from process migration are not so certain, either. "You can't just assume you will get a smaller die at 90 nm," warned Ata Khan, director of innovation at Philips Semiconductors. "Most of our ARM7TDMI-based MCUs are already pad-limited at 140 nm, so going forward is not going to shrink them."
Equally important is the danger that the characteristics of the new process, tuned as it is likely to be for very high logic density and high performance, may not serve the needs of MCU users. Performance at 90 nm is not likely to be much better than at 130 or even 150 nm once proper measures have been taken to control power. And in any case, for most applications raw performance at the larger geometries is probably already in excess of what you need.
Worse, there may be serious electrical considerations. MCUs implemented in 90 nm will require core voltages in the range of 1 V. This voltage may not be available in existing embedded designs, and almost certainly not at the level or regulation that a high-performance 90-nm process would require.
What is available is a plethora of I/Os at 3.3 or even 5 V, plus large-swing analog signals that need to be interfaced directly to the MCU. And the 90-nm processes will not tolerate those voltages without special provisions.
NEC Corp. is using the density of 90 nm to attack a very specific market: content processing on handheld devices. This strategy has a number of advantages. To begin with, content processing-video encoding and decoding, 3-D graphics, security and authentication, game dynamics and the like-can soak up as much computing power as any vendor is willing to offer them. So the ability to run an MCU core fast, and to add more cores, is valuable. So is the ability to put a large amount of SRAM on the die without having the cost explode.
Additionally, because the chip will be used in any environment that already has other low-voltage parts and that doesn't require interfaces to high-voltage signals, the voltage limitations of the process are not serious design issues.
These considerations are reflected in the chip NEC described at the International Solid-State Circuits Conference. The MP211 multicore system LSI includes three ARM926 CPU cores, a DSP core, security and graphics accelerators, and a passel of interfaces.
A similar theme was sounded at the same conference by Fujitsu Laboratories Ltd., aiming for the slightly less power-constrained home multimedia market. In this case Fujitsu used its 90-nm process to get four of its FR550 VLIW CPU cores, bus controllers and extensive direct memory access (DMA) logic on one die.
Internal buses were a serious design consideration for both NEC and Fujitsu. "In the MP211, the interprocessor bus has been tuned to the specific bandwidth and connectivity requirements of the applications we envision," said Masao Fukuma, vice president and executive general manager of the System Devices Research Lab at NEC. "In addition, the bus includes hardware to enforce isolation between the processors so that all but one of the cores runs in a physically secure environment."
Similarly, the Fujitsu chip is built around a central on-chip system bus with a highly complex DMA engine dedicated to transfers between on-chip memories. This design takes nearly as much die area as one of the FR550 CPU cores. There is a separate DMA engine and a sophisticated SDRAM controller for transactions with external memory.
But when it comes to media-rich applications, is MCU technology diverging from the traditional embedded designs? Not if the Philips LPC3000 family is any indication. This is in every sense a traditional microcontroller from a company with a long history and deep product line in the MCU business. It incorporates a single ARM926, and could be described on a thumbnail as an MCU implementation, sans DSP hardware, of the Nexperia architecture.
Like the other devices, the LPC3000 family will use a 90-nm process. But as a traditional MCU, it faces different challenges. Speed is not one of them.
Where the Fujitsu FR550 processors, for example, are rated at 533 MHz, the LPC3000's ARM core is running at only 200 MHz-more than enough for the anticipated applications. There are 64 kbytes of on-chip SRAM, but the on-chip, two-transistor flash for which Philips has been noted of late is absent. The 90-nm flash process has not taped out yet, so that will have to wait. There is the usual assortment of MCU on-chip peripherals, including a 10-bit A/D converter-no small challenge in the 90-nm process.
But Philips had to make some major adaptations to allow the 90-nm technology to live happily ever after with the realities of MCUs. Major changes to the comprehensive on-chip debug logic was one of them. "It would have required 21 pins to move trace data off of the chip in real-time at these speeds," Khan explained. "So we opted instead for an on-chip trace buffer large enough to capture a meaningful number of cycles." Voltages are also an issue. The MCU needed a 3.3-V pad ring to be useful in real applications. But the gate oxide of the 90-nm transistors, which normally run at slightly over 1 V, would not withstand that. Philips moved to a dual-oxide-thickness process to support the pad ring.
Power issues, meanwhile, led Philips to use the LP version of the 90-nm process. "It gives us leakage comparable to what we had at 0.18 micron," Khan said, "but to get there we had to use high-threshold transistors." Since speed was not an issue, that didn't present a problem. And there was a matching opportunity. The 90-nm thin-oxide core can be operated at very low voltage-as little as 0.9 V-and still hit 13 MHz, or about 20 Mips through the ARM core. At that voltage it still draws only about 5 milliamps.
So it appears that 90-nm technology, with some care, can produce a conventional MCU. In Philips' eyes, it can also produce an interesting road map. The LPC3000 implements the multilayer AHB bus-ARM's answer to a crossbar switch interconnect fabric. "This is probably overkill on a single-processor system today," Khan said. "But it will be valuable going forward."
Are multicore, Gips-level MCUs next? The applications will be there. And with 90 nm, the performance will be too, despite the obstacles.