San Jose, Calif. The SY8984x multiplexer family offers a non-PLL clock switchover circuit that guarantees no runt pulses, when the inputs are switched. Optimized for networking system designs, this multiplexer family includes options with integrated fanout buffers and rise/fall times of 250 ps for LVDS and LVPECL outputs and 150 psfor CML outputs. Jitter performance is guaranteed to be less than 10 ps peak-to-peak while output-to-output skew is slated to be less than 25 ps within the multiplexers. The multiplexers operate from a 2.5- or 3.3-V supply.
Pricing: Starts at $2.55 in 1000-unit quantities