Hillsboro, Ore. Lattice Semiconductor Corp. has upgraded its ispLEVER-Starter 5.0 design tools, which can now be downloaded from the company's web site at no charge.
Lattice is offering ispLEVER-Starter 5.0 free of charge to promote evaluation of its recently announced ispLEVER 5.0 programmable logic design tool suite. It uses the same interface and design flow as ispLEVER 5.0, and can be used to take a design from concept to device programming. Like previous ispLEVER-Starter design tools, the latest version, 5.0, supports all Lattice ispXPGA, field programmable gate arrays (FPGA), complex programmable logic devices (CPLD), ispGDX and SPLD devices.
The PC-based ispLEVER-Starter 5.0 tools now include design support for LatticeEC FPGAs and LatticeECP-DSP6 devices.
The LatticeEC family consists of seven family members ranging in density from 1.5-K to 33K LUTs. "With design support for the entire product line so accessible, every design engineer worldwide will be able to evaluate our technology and its advantages first-hand," said Stan Kopec, Lattice vice president of corporate marketing.
The ispLEVER-Starter 5.0 offers significant performance improvements over previous design tool versions. They include an increase in FIFO performance by 50 to 70%; "substantially faster" LatticeECP DSP block performance; and a 5% reduction in device resources.
A full list of ispLEVER 5.0 features and enhancements can be seen at www.latticesemi.com/products/devtools/software/isplever50.cfm
The ispLEVER-Starter 5.0 design tools can be downloaded from www.latticesemi.com/starter
Lattice Semiconductor Corp., 1-503-268-8000, www.latticesemi.com