SAN FRANCISCO Celoxica on Monday (May 23) released the fourth generation of its DK Design Suite, DK4, which the company said contains major enhancements and "resets the bar" for C-synthesis performance.
The new version's advanced memory utilization increases design capacity and speeds synthesis execution, synthesis optimization and improves quality of results, the company said. Enhancements to the tool ease the software-to-silicon process and link electronic system level (ESL) to physical system-on-chip (SoC) design, according to Celoxica (Abingdon, England).
DK4 introduces new VHDL and Verilog output optimizations for interfacing with Synopsys Inc.'s Design Compiler. In addition to register transfer-transfer-level (RTL) input for the SoC flow, DK4 also supports automatic scripting for SoC test bench generation, Celoxica said, bridging the gap between ESL and latest SoC physical design and verification flows.
The advanced memory utilization technology in DK4 supports designer productivity with synthesis of larger and more complex designs 30-50 percent faster than previous versions of the tool, the company said, enabling DK4 to produce field-programmable gate array (FPGA) implementations directly from large software models.
The silicon coverage in DK4 has also been extended to include the latest Xilinx devices, Celoxica said.
Celoxica said Version 4 of the Celoxica DK Design Suite is available for delivery in July in various package options ranging in list price from $10,000 to $80,000. The DK Design Suite is available on Windows and Linux operating systems.